mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
104 lines
6.1 KiB
Python
104 lines
6.1 KiB
Python
import logging
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import os
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import yaml
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import json
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class CaravelConfig():
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def __init__(self, config, projects, modules_yaml_name: str):
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self.config = config
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self.projects = projects
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self.script_dir = os.path.dirname(os.path.realpath(__file__))
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self.modules_yaml_name = modules_yaml_name
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# instantiate inside user_project_wrapper
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def instantiate(self):
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# build the blackbox_project_includes.v file - used for blackboxing when building the GDS
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with open('verilog/blackbox_project_includes.v', 'w') as fh:
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for project in self.projects:
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fh.write(f'`include "gl/{project.get_gl_verilog_filename()}"\n')
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# build complete list of filenames for sim
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with open('verilog/includes/includes.rtl.caravel_user_project', 'w') as fh:
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_top.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_ctrl.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_mux.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_user_module.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_buf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_dfrbp.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_diode.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_inv.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_mux4.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_tbuf_pol.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_tbuf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_zbuf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/cells.v\n')
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# for project in self.projects:
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# fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{project.get_top_verilog_filename()}\n')
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with open('verilog/includes/includes.rtl.caravel_user_project.openlane2', 'w') as fh:
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/ol2/tt_top/user_project_wrapper.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_top.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_ctrl.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_mux.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_user_module.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_buf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_dfrbp.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_diode.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_inv.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_mux4.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tbuf_pol.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tbuf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tie.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_zbuf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/cells.v\n')
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# for project in self.projects:
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# fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{project.get_top_verilog_filename()}\n')
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# build GL includes
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with open('verilog/includes/includes.gl.caravel_user_project', 'w') as fh:
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fh.write('-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_ctrl.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_mux.v\n')
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for project in self.projects:
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fh.write(f'-v $(USER_PROJECT_VERILOG)/gl/{project.get_gl_verilog_filename()}\n')
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with open(self.modules_yaml_name, 'r') as modules_file:
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module_config = yaml.safe_load(modules_file)
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configured_macros = set(map(lambda mod: mod['name'], module_config['modules']))
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logging.info(f"found {len(configured_macros)} preconfigured macros: {configured_macros}")
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for project in self.projects:
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if project.unprefixed_name not in configured_macros:
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module_config['modules'].append({'name': project.unprefixed_name})
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with open('tt-multiplexer/cfg/modules.yaml', 'w') as mux_modules_file:
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yaml.dump(module_config, mux_modules_file)
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res = os.system("make -C tt-multiplexer gensrc")
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if res != 0:
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logging.error("Failed to generate multiplexer placement configuration")
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exit(1)
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mux_index = {}
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mux_index_reverse = {}
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with open('tt-multiplexer/cfg/modules_placed.yaml') as placed_modules_file:
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placed_modules = yaml.safe_load(placed_modules_file)
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for module in placed_modules['modules']:
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mux_address = (module['y'] << 5) + module['x']
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module_name = 'tt_um_' + module['name']
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mux_index[mux_address] = module_name
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mux_index_reverse[module_name] = mux_address
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for project in self.projects:
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if project.top_module not in mux_index_reverse:
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logging.error(f"no placement found for {project}!")
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exit(1)
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project.mux_address = mux_index_reverse[project.top_module]
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with open('mux_index.json', 'w') as mux_index_file:
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json.dump(mux_index, mux_index_file)
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def list(self):
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for project in self.projects:
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logging.info(project)
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