mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
71 lines
3.7 KiB
Python
71 lines
3.7 KiB
Python
import logging
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import json
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import os
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class CaravelConfig():
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def __init__(self, config, projects, num_projects):
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self.config = config
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self.projects = projects
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self.num_projects = num_projects
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self.script_dir = os.path.dirname(os.path.realpath(__file__))
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# update caravel config
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def create_macro_config(self):
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with open(os.path.join(self.script_dir, 'caravel_template', 'upw_config.json')) as fh:
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caravel_config = json.load(fh)
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logging.info("GDS and LEF")
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lef_prefix = "dir::../../lef/"
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gds_prefix = "dir::../../gds/"
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for project in self.projects:
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if not project.is_fill():
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caravel_config["EXTRA_LEFS"].append(lef_prefix + project.get_macro_lef_filename())
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caravel_config["EXTRA_GDS_FILES"].append(gds_prefix + project.get_macro_gds_filename())
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with open("openlane/user_project_wrapper/config.json", 'w') as fh:
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json.dump(caravel_config, fh, indent=4)
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# instantiate inside user_project_wrapper
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def instantiate(self):
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# build the blackbox_project_includes.v file - used for blackboxing when building the GDS
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with open('verilog/blackbox_project_includes.v', 'w') as fh:
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for project in self.projects:
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if not project.is_fill():
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fh.write(f'`include "gl/{project.get_gl_verilog_filename()}"\n')
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# build complete list of filenames for sim
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with open('verilog/includes/includes.rtl.caravel_user_project', 'w') as fh:
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_top.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_ctrl.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_mux.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_user_module.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_buf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_dfrbp.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_diode.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_inv.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_mux4.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_tbuf_pol.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_tbuf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_zbuf.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/rtl/cells.v\n')
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for project in self.projects:
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if not project.is_fill():
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fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{project.get_top_verilog_filename()}\n')
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# build GL includes
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with open('verilog/includes/includes.gl.caravel_user_project', 'w') as fh:
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fh.write('-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_ctrl.v\n')
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fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_mux.v\n')
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for project in self.projects:
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if not project.is_fill():
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fh.write(f'-v $(USER_PROJECT_VERILOG)/gl/{project.get_gl_verilog_filename()}\n')
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def list(self):
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for project in self.projects:
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if not project.is_fill():
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logging.info(project)
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