mirror of
https://github.com/TinyTapeout/tt-support-tools.git
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266 lines
11 KiB
YAML
266 lines
11 KiB
YAML
# ---------------------------------------------------------------------------
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# Tiny Tapeout product datasheet — all copy, numbers and colours.
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#
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# Edit this file, then rebuild:
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# python3 docs/product/build.py
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#
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# Notes for editing:
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# - Every text field is rendered as raw HTML, so <b>, <br> and <a href="...">
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# work anywhere. Write a literal ampersand as &.
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# - Table `style` tokens set cell formatting, space separated:
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# name bold, no wrapping (first column of most tables)
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# mono bold + tabular figures (dimensions, values, signal names)
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# num tabular figures (aligned digits)
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# price bold red + no wrapping (pricing column)
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# dim greyed out (em dashes, secondary text)
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# center centre aligned
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# - Table rows must have the same number of cells as there are columns.
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# ---------------------------------------------------------------------------
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doc:
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title: Tiny Tapeout — Datasheet
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wordmark: Tiny Tapeout
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wordmark_sub: SHARED SILICON ASIC SHUTTLE
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tag: DATASHEET
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ref: DOC TT-DS-2026 · REV A
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page2_title: Electrical & Mechanical Specifications
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# Colours and the two page-level type sizes. Everything else scales from these.
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theme:
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navy: "#040371" # header bars and table header rows
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red: "#ec3013" # accent: labels, rules, prices
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ink: "#141414" # body text
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ink_mid: "#55545f" # secondary text
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ink_faint: "#86858f" # captions, dashes
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ground: "#f2f1f4" # zebra stripe on tables
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rule: "#c9c8d0" # thin rules
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rule_hard: "#141414" # 2px section rules
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heading_size: 30pt # page 1 headline
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body_size: 8.3pt # feature and FAQ body text
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assets:
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# Relative to docs/product/assets/. Swap either file and rebuild.
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photo: demoboard.jpg
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font: archivo.woff2
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# --------------------------------------------------------------------------
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# PAGE 1
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# --------------------------------------------------------------------------
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hero:
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eyebrow: Shared multi-project chip · SKY130 / SG13G2 / GF180MCU
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heading: From idea to chip design in minutes
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body: >-
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Tiny Tapeout makes it more accessible than ever to get your designs manufactured on a real chip.
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Submit from a
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GitHub repository and we handle integration, tapeout, packaging and delivery.
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photo_alt: Tiny Tapeout ETR demoboard with a QFN-64 packaged ASIC on a breakout board
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photo_caption: Demoboard with QFN-64 packaged die on breakout carrier.
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features:
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- kicker: 01 · Toolchain
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title: Local tool install optional
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body: >-
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The whole flow can run in GitHub Actions. Push your repository and your design
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is hardened in the cloud — nothing to install, no licences to buy.
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- kicker: 02 · Languages
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title: HDL agnostic
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body: >-
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Any language that can produce Verilog RTL. Project templates and CI are
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supplied for Verilog, with community provided VHDL and Chisel.
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- kicker: 03 · I/O
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title: 26 pins, plus analog
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body: >-
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Clock, reset, 8 dedicated inputs, 8 dedicated outputs and 8 bidirectional
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pins — plus up to 6 analog pins where the process allows.
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- kicker: 04 · Process
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title: Three PDKs
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body: >-
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SkyWater SKY130, IHP sg13g2 and GlobalFoundries gf180mcu. Open-source PDKs
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running multiple times per year.
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- kicker: 05 · Hardware
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title: Demoboard available
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body: >-
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An optional RP2350-based demoboard carries your packaged chip and selects
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any project on the die over USB.
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- kicker: 06 · Flexibility
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title: Bring your own flow
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body: >-
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Harden with the supplied open-source LibreLane flow, or use your own tools
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entirely — the minimum submission is GDS + LEF.
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pricing:
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heading: Pricing
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note: INDICATIVE FROM-PRICES · EUR
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columns:
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- {label: Item, width: "27%", style: name}
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- {label: What it buys you}
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- {label: From, width: "26%", style: price}
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rows:
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- ["1 tile",
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"Roughly 1,000 standard cells of silicon area. Physical dimensions vary by PDK — see page 2.",
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"€70"]
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- ["Analog pin",
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"Multiplexed analog pad access for mixed signal designs. Minimum project size of 2 tiles applies.",
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"€100 <span class=\"t-sub\">/ pin</span>"]
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- ["Demoboard PCB",
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"Optional add-on: your packaged chip, an RP2350 demoboard and a breakout board.",
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"€100 <span class=\"t-sub\">first 80 boards for individuals are subsidised</span><br>€300 <span class=\"t-sub\">academic & industry</span>"]
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footnote: >-
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<b>Silicon area and the demoboard are billed separately.</b> Buying area gets
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your design manufactured on the wafer — on its own it does not get you a
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physical chip. To hold your chip in your hand, add the demoboard PCB. Confirm
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current figures at
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<b><a href="https://app.tinytapeout.com/calculator">app.tinytapeout.com/calculator</a></b>.
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faq:
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heading: Frequently asked Questions
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note: FULL FAQ AT TINYTAPEOUT.COM/FAQ
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items:
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- q: How long until I get my chip?
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a: >-
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Fabrication takes 6–9 months, then boards are assembled, tested and
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shipped. Check <a href="https://app.tinytapeout.com/chips">tinytapeout.com/chips</a> for the schedule.</b>.
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- q: Do I need chip design experience?
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a: >-
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No. Getting started documentation on the website and help on the Discord community helps beginners get started.
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Thousands of past projects are public to learn from.
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- q: What do I actually receive?
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a: >-
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Area alone gets your design onto the wafer. Add the demoboard to receive a
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packaged chip, an RP2350 demoboard and a breakout board. Bare chips are not available separately.
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- q: Which processes can I use?
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a: >-
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SkyWater SKY130 (130 nm), IHP sg13g2 (130 nm BiCMOS) and GlobalFoundries
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gf180mcu (180 nm), each on its own shuttle schedule.
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- q: Is it only open to individuals?
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a: >-
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No. Universities, schools and companies run group submissions, and dozens
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of institutions already teach with Tiny Tapeout.
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- q: What are the licence terms?
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a: >-
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Every design is published publicly under Apache-2.0. The minimum
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submission is GDS + LEF, produced with any toolchain you like.
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institutions:
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label: Taught and used at
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items:
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- Carnegie Mellon University
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- New York University
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- UC Santa Cruz
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- UC San Diego
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- San Jose State University
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- Oklahoma State University
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- Technical University of Denmark
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- Linköping University
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- Graz University of Technology
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# --------------------------------------------------------------------------
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# PAGE 2
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# --------------------------------------------------------------------------
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process:
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heading: Process & fabrication
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note: TILE DIMENSIONS PER PDK
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columns:
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- {label: PDK, width: "19%", style: name}
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- {label: Foundry, width: "21%"}
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- {label: Node, width: "17%", style: num}
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- {label: 1×1 tile area, width: "25%", style: mono}
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- {label: Package}
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rows:
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- ["SKY130A", "SkyWater", "130 nm", "161.00 × 111.52 µm", "QFN-64"]
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- ["ihp-sg13g2", "IHP", "130 nm BiCMOS", "202.08 × 154.98 µm", "QFN-64"]
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- ["gf180mcuD", "GlobalFoundries", "180 nm", "346.64 × 160.72 µm", "QFN-64"]
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footnote: >-
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One tile holds approximately <b>1,000 standard cells</b>. Larger designs are
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built from multi-tile blocks from 1×2 up to 8×4; the available sizes differ
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per PDK. Analog projects require a minimum height of 2 tiles.
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ratings:
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heading: Absolute maximum ratings
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note: DIGITAL I/O
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columns:
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- {label: Parameter, width: "40%", style: name}
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- {label: Min, width: "13%", style: num}
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- {label: Typ, width: "13%", style: num}
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- {label: Max, width: "13%", style: num}
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- {label: Unit}
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rows:
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- ["I/O supply voltage", "1.71", "3.30", "5.50", "V"]
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- ["Input frequency", "—", "—", "66", "MHz"]
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- ["Output toggle frequency", "—", "—", "33", "MHz"]
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- ["Output drive strength, source/sink", "—", "4", "—", "mA"]
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- ["Demoboard clock generator", "1", "—", "66.5 M", "Hz"]
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- ["Pad-to-tile round-trip latency", "—", "—", "20", "ns"]
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- ["Clock insertion delay, pad to logic", "—", "—", "10", "ns"]
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- ["Pin-to-pin latency variance", "—", "—", "2", "ns"]
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footnote: >-
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Characterised on <b>SKY130A</b> using the <b>sky130_ef_io_gpiov2_pad</b> cell;
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ratings differ per PDK. Inputs are <b>not 5 V tolerant</b> despite the supply
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range. Full per-process figures at
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<b><a href="https://tinytapeout.com/specs/">tinytapeout.com/specs</a></b>.
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gpio:
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heading: GPIO pin map
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columns:
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- {label: Signal, width: "34%", style: mono}
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- {label: Width, width: "14%", style: num center}
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- {label: Direction, width: "22%"}
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- {label: Function}
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rows:
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- ["clk", "1", "Input", "Clock"]
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- ["rst_n", "1", "Input", "Reset, active low"]
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- ["ui_in[7:0]", "8", "Input", "General purpose"]
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- ["uo_out[7:0]", "8", "Output", "General purpose"]
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- ["uio[7:0]", "8", "Bidirectional", "Per-pin direction control"]
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linkline: >-
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26 I/O PINS TOTAL ·
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<b><a href="https://tinytapeout.com/specs/gpio/">TINYTAPEOUT.COM/SPECS/GPIO</a></b>
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analog:
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heading: Analog I/O
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note: OPTIONAL
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columns:
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- {label: Parameter, style: name}
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- {label: Value, width: "34%", style: mono}
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rows:
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- ["Analog pins, maximum", "6 · ua[0:5]"]
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- ["Series resistance, pad to project", "< 500 Ω"]
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- ["Parasitic capacitance", "< 5 pF"]
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- ["Current per pin, maximum", "4 mA"]
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- ["VDPWR digital supply", "1.8 V"]
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- ["VAPWR analog supply", "3.3 V"]
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linkline: >-
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ALLOCATED IN ORDER ·
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<b><a href="https://tinytapeout.com/specs/analog/">TINYTAPEOUT.COM/SPECS/ANALOG</a></b>
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ordering:
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heading: Ordering information
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note: APP.TINYTAPEOUT.COM/CALCULATOR
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headless: true # no header row on this table
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columns:
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- {width: "27%", style: name}
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- {}
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rows:
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- ["Shuttle cadence",
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"Several shuttles per year across the three processes. Check <a href="https://app.tinytapeout.com/chips">tinytapeout.com/chips</a> for the schedule"]
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- ["Lead time",
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"6–9 months in fabrication, then assembly, test and fulfilment."]
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- ["Deliverable",
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"Silicon area only for remote or shared test, or area plus the demoboard kit: packaged chip, RP2350 demoboard and breakout board."]
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- ["Design tools",
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"Supplied open-source LibreLane flow running in GitHub Actions, or any toolchain of your own."]
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- ["Minimum submission",
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"GDS + LEF in a public repository, licensed Apache-2.0."]
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disclaimer:
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label: Disclaimer
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body: >-
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Specifications are indicative and subject to change between shuttles.
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Electrical characteristics are quoted for the SKY130A process unless stated
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otherwise — consult tinytapeout.com/specs for the process you intend to use.
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Pricing is indicative; confirm current figures with the calculator before
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ordering. Tiny Tapeout devices are educational and prototyping parts, and are
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not qualified for safety-critical, medical or automotive use.
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