mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
Pat Deegan
89ad9bfa93
* TT FPGA tool, prelim import * config.ini manager, prelim * bitstream uploads and FPGA config.ini management Contributed by @psychogenic, with minor edits by @htfab
355 lines
10 KiB
Python
Executable File
355 lines
10 KiB
Python
Executable File
#!/usr/bin/env python3
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"""
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tt_fpga -- FPGA breakout management tool
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@author: Pat Deegan
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In a project based on a TT template, with a configured info.yaml, all you need
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is to run
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python tt/tt_fpga.py harden
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to generate a bitstream in build/. Then
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python tt/tt_fpga.py configure --upload
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will make the bitstream available through the tt.shuttle object in the DB REPL.
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You may also set this as the default project to load on startup and/or set the
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auto-clocking rate through the configure command, e.g.
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python tt/tt_fpga.py configure --upload --set-default --clockrate 1000
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to do all three at once.
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If you have no info.yaml template, the script will work anyway. But you'll need
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to specify more command line arguments.
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See
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python tt/tt_fpga.py harden --help
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and
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python tt/tt_fpga.py configure --help
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"""
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import argparse
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import logging
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import os
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import subprocess
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import sys
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from project import SCRIPT_DIR, Project
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from tt_db_config import DefaultPort, TTDBConfig
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from tt_logging import setup_logging
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CommandHarden = "harden"
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CommandConfig = "configure"
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def getParser():
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parser = argparse.ArgumentParser(
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description="TT FPGA tool",
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# formatter_class=argparse.RawDescriptionHelpFormatter
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)
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parser.add_argument("--project-dir", help="location of the project", default=".")
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# parser.add_argument("--yaml", help="the project's yaml configuration file", default="info.yaml")
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# Global options (available to all subcommands)
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parser.add_argument(
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"--debug",
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metavar="LEVEL",
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help="debug logging",
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action="store_const",
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dest="loglevel",
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const=logging.DEBUG,
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default=logging.INFO,
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)
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# Create subparsers
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subparsers = parser.add_subparsers(
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dest="command",
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required=True, # make subcommand mandatory
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help="Available commands",
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)
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# ----------------------
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# Subcommand: hardening
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# ----------------------
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harden = subparsers.add_parser(CommandHarden, help="Run hardening process")
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harden.add_argument(
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"--name",
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metavar="FILE",
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help="Output file and project name (default: top_module name)",
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default="",
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)
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harden.add_argument(
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"--breakout-target",
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help="Select target breakout: classic (TT04), fabricfox (TT ETR db) default: fabricfox",
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choices=["classic", "fabricfox"],
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default="fabricfox",
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)
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harden.add_argument(
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"--source_dir",
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metavar="DIR",
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help="Directory containing source verilog files (default from info.yaml)",
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)
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harden.add_argument(
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"--source",
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action="append",
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metavar="FILE",
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help="Source file(s) to harden (specify multiple times for multiple source files, default from info.yaml)",
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)
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harden.add_argument(
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"--top_module",
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metavar="TOP",
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help="Name of the top module (default from info.yaml)",
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)
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# ----------------------
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# Subcommand: configuration
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# ----------------------
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config = subparsers.add_parser(
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CommandConfig, help="Upload bitstream and manage configuration"
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)
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config.add_argument(
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"--port",
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metavar="COMPORT",
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type=str,
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default=DefaultPort,
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help=f"Port for uploads (default: {DefaultPort})",
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)
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config.add_argument(
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"--set-default",
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action="store_true",
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help="set this project as the default on startup",
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)
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config.add_argument(
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"--upload", action="store_true", help="upload the bitstream.bin from build/"
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)
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config.add_argument(
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"--clockrate",
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metavar="RATE",
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type=int,
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help="Clock rate in Hz",
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)
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config.add_argument(
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"--name",
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metavar="FILE",
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help="Output file and project name (default: top_module name)",
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default="",
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)
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return parser
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def die_with_error(msg):
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print(msg)
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sys.exit(2)
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class TTFPGA:
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def __init__(self, proj: Project | None, args):
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self.project = proj
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self.args = args
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def get_name(self):
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base_name = self.args.name
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if not len(base_name):
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if (
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"top_module" in self.args
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and self.args.top_module is not None
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and len(self.args.top_module)
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):
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return self.args.top_module
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if self.project is not None:
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base_name = self.project.info.top_module
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if not len(base_name): # shouldn't happen
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base_name = "tt_fpga_project"
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return base_name
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@property
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def bitstream_filename(self):
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return f"{self.get_name()}.bin"
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@property
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def top_module(self):
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if "top_module" in self.args and self.args.top_module:
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# command line overrides yaml
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return self.args.top_module
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if self.project is not None:
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return self.project.info.top_module
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if "top_module" in self.args:
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if not self.args.top_module:
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die_with_error("No project yaml, must specify top_module")
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else:
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return None
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return self.args.top_module
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@property
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def source_dir(self):
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if self.args.source_dir:
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# command line overrides yaml
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return self.args.source_dir
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if self.project is not None:
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return self.project.src_dir
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if not self.args.source_dir:
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die_with_error("No project yaml, must specify source_dir")
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return self.args.source_dir
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@property
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def local_dir(self):
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if self.project is not None:
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return self.project.local_dir
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return os.path.realpath(self.args.project_dir)
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@property
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def sources(self):
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if self.args.source and len(self.args.source):
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# command line overrides yaml
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return self.args.source
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if self.project is not None:
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return self.project.sources
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if not self.args.source:
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die_with_error(
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"No project yaml, must specify --source A.v --source B.v ..."
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)
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# print(self.args.source)
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return self.args.source
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def create_fpga_bitstream(self):
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logging.info(f"Creating FPGA bitstream for {self.project}")
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target_map = {
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"classic": {
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"pcf": "tt_fpga_top.pcf",
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},
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"fabricfox": {
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"pcf": "tt_fpga_fabricfoxv2.pcf",
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},
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}
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args = self.args
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pcf_file = target_map[args.breakout_target]["pcf"]
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base_name = self.get_name()
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with open(os.path.join(SCRIPT_DIR, "fpga/tt_fpga_top.v"), "r") as f:
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top_module_template = f.read()
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with open(os.path.join(self.source_dir, "_tt_fpga_top.v"), "w") as f:
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f.write(top_module_template.replace("__tt_um_placeholder", self.top_module))
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build_dir = os.path.join(self.local_dir, "build")
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os.makedirs(build_dir, exist_ok=True)
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sources = [os.path.join(self.source_dir, src) for src in self.sources]
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source_list = " ".join(sources)
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yosys_cmd = f"yosys -l {build_dir}/01-synth.log -DSYNTH -p 'read_verilog -sv src/_tt_fpga_top.v {source_list}; synth_ice40 -top tt_fpga_top -json {build_dir}/{base_name}.json'"
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logging.debug(yosys_cmd)
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p = subprocess.run(yosys_cmd, shell=True)
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if p.returncode != 0:
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logging.error("synthesis failed")
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exit(1)
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seed = os.getenv("TT_FPGA_SEED", "10")
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freq = os.getenv("TT_FPGA_FREQ", "12")
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nextpnr_cmd = f"nextpnr-ice40 -l {build_dir}/02-nextpnr.log --pcf-allow-unconstrained --seed {seed} --freq {freq} --package sg48 --up5k --asc {build_dir}/{base_name}.asc --pcf {SCRIPT_DIR}/fpga/{pcf_file} --json {build_dir}/{base_name}.json"
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logging.debug(nextpnr_cmd)
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p = subprocess.run(nextpnr_cmd, shell=True)
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if p.returncode != 0:
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logging.error("placement failed")
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exit(1)
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icepack_cmd = f"icepack {build_dir}/{base_name}.asc {build_dir}/{base_name}.bin"
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logging.debug(icepack_cmd)
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p = subprocess.run(icepack_cmd, shell=True)
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if p.returncode != 0:
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logging.error("bitstream creation failed failed")
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exit(1)
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logging.info(f"Bitstream created successfully: {build_dir}/{base_name}.bin")
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def yaml_file_exists(args):
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return os.path.exists(os.path.join(os.path.realpath(args.project_dir), "info.yaml"))
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def main():
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parser = getParser()
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args = parser.parse_args()
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setup_logging(args.loglevel)
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if args.command != CommandHarden and args.command != CommandConfig:
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parser.print_help()
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sys.exit(1)
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project = None
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if yaml_file_exists(args):
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project = Project(
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0, "unknown", args.project_dir, pdk="fpgaUp5k", is_user_project=True
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)
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project.post_clone_setup()
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fpga = TTFPGA(project, args)
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if args.command == CommandHarden:
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fpga.create_fpga_bitstream()
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elif args.command == CommandConfig:
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proj_name = fpga.get_name()
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bitstream_name = f"{proj_name}.bin"
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fname = f"build/{bitstream_name}"
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if not os.path.exists(fname):
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print(f"Can't find {fname}")
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sys.exit(3)
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ttdbconf = TTDBConfig(args.port)
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if args.upload:
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print(f"Uploading {fname}")
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ttdbconf.write_file(fname, f"/bitstreams/{bitstream_name}")
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if args.set_default or args.clockrate is not None:
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cnf = ttdbconf.get_config_ini()
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if args.set_default:
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cnf.set_default_project(proj_name)
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if args.clockrate is not None:
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cnf.set_project_clockrate(proj_name, args.clockrate)
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cnf.save() # save local file
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# upload that config.ini
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ttdbconf.upload_config_ini(cnf.filepath, do_reset=False)
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ttdbconf.reset() # restart
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if not (args.upload or args.set_default or args.clockrate):
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print(
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"Did nothing. Use configure with --upload, --set-default and/or --clockrate"
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)
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if __name__ == "__main__":
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main()
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