TinyTapeout/tt-support-tools
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tt-support-tools/def/tt_block_1x1_pg.def
T
Uri Shaked 3d87be1a9c feat(def): update tt_block def files for tt08 
The pin positions have changed to keep space for the analog supply voltage gating transistor
2024-06-09 08:42:59 +03:00

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VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 161000 111520 ) ;
ROW ROW_0 unithd 2760 2720 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_1 unithd 2760 5440 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_2 unithd 2760 8160 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_3 unithd 2760 10880 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_4 unithd 2760 13600 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_5 unithd 2760 16320 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_6 unithd 2760 19040 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_7 unithd 2760 21760 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_8 unithd 2760 24480 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_9 unithd 2760 27200 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_10 unithd 2760 29920 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_11 unithd 2760 32640 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_12 unithd 2760 35360 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_13 unithd 2760 38080 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_14 unithd 2760 40800 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_15 unithd 2760 43520 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_16 unithd 2760 46240 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_17 unithd 2760 48960 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_18 unithd 2760 51680 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_19 unithd 2760 54400 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_20 unithd 2760 57120 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_21 unithd 2760 59840 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_22 unithd 2760 62560 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_23 unithd 2760 65280 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_24 unithd 2760 68000 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_25 unithd 2760 70720 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_26 unithd 2760 73440 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_27 unithd 2760 76160 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_28 unithd 2760 78880 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_29 unithd 2760 81600 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_30 unithd 2760 84320 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_31 unithd 2760 87040 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_32 unithd 2760 89760 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_33 unithd 2760 92480 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_34 unithd 2760 95200 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_35 unithd 2760 97920 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_36 unithd 2760 100640 N DO 338 BY 1 STEP 460 0 ;
ROW ROW_37 unithd 2760 103360 FS DO 338 BY 1 STEP 460 0 ;
ROW ROW_38 unithd 2760 106080 N DO 338 BY 1 STEP 460 0 ;
TRACKS X 230 DO 350 STEP 460 LAYER li1 ;
TRACKS Y 170 DO 328 STEP 340 LAYER li1 ;
TRACKS X 170 DO 473 STEP 340 LAYER met1 ;
TRACKS Y 170 DO 328 STEP 340 LAYER met1 ;
TRACKS X 230 DO 350 STEP 460 LAYER met2 ;
TRACKS Y 230 DO 242 STEP 460 LAYER met2 ;
TRACKS X 340 DO 237 STEP 680 LAYER met3 ;
TRACKS Y 340 DO 164 STEP 680 LAYER met3 ;
TRACKS X 460 DO 175 STEP 920 LAYER met4 ;
TRACKS Y 460 DO 121 STEP 920 LAYER met4 ;
TRACKS X 1700 DO 47 STEP 3400 LAYER met5 ;
TRACKS Y 1700 DO 33 STEP 3400 LAYER met5 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 143980 111020 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 146740 111020 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141220 111020 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 138460 111020 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 135700 111020 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 132940 111020 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 130180 111020 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 127420 111020 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 124660 111020 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121900 111020 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 119140 111020 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 116380 111020 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 113620 111020 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110860 111020 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 108100 111020 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 105340 111020 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102580 111020 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 99820 111020 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 97060 111020 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 50140 111020 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 47380 111020 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 44620 111020 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41860 111020 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 39100 111020 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 36340 111020 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33580 111020 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 30820 111020 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72220 111020 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 69460 111020 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 66700 111020 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 63940 111020 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 61180 111020 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 58420 111020 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 55660 111020 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52900 111020 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 94300 111020 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91540 111020 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 88780 111020 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 86020 111020 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83260 111020 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 80500 111020 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 77740 111020 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 74980 111020 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
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