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116 lines
4.2 KiB
Markdown
116 lines
4.2 KiB
Markdown
# Toplevel STA and Spice analysis for TinyTapeout-02 and 03.
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Contributed by J. Birch 22 March 2023
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## Introduction
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TinyTapeout is built using the OpenLane flow and consists of three major components:
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1) up to 250 user designs with a common interface, each of which has been composed using the OpenLane flow,
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2) a scanchain block that is instanced for each user design to provide input data and to sink output data,
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3) a scan chain controller.
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The OpenLane flow allows for timing analysis of each of these individual blocks but does not provide for
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analysis of the assembly of them, which leaves potential holes in timing that could cause failures.
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This work allows a single design to be assembled out of the sub-blocks and this can then be submitted to
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STA for analysis.
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In addition, an example critical path (for the clock that is passed along the scanchain) is created using
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a Python script so that it can be run through SPICE.
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## GitHub action
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The [STA github action](.github/workflows/sta.yaml) automatically runs the STA when the repository is updated.
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## Prerequisites
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To run STA, the following files need to be available:
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1) a gate level verilog netlist of the top level design (verilog/rtl/user_project_wrapper.v)
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2) a gate level verilog netlist for each sub-block (verilog/rtl/)
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3) a SPEF format parasitics file for the top level wiring (spef/)
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4) a SPEF format parasitics file for each sub-block (spef/)
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5) the relevant SkyWater libraries for STA analysis - installed with the PDK
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6) OpenSTA 2.4.0 (or later) needs to be on the PATH. rundocker.sh shows how to use STA included in the OpenLane docker
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7) python3.9 or later
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8) verilog parser (pip3 install verilog-parser)
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9) a constraints file (sta_top/top.sdc)
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## Assumptions
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* all of the Verilog files are in a single directory
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* all of the SPEF files are in a single directory
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## Issues
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The Verilog parser has two bugs: it does not recognise 'inout' and it does not cope
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with escaped names (starting with a '\'). Locally this has been fixed but to use the
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off-the-shelf parser we preprocess the file to change inout to input and remove the escapes and
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substitute the [nnn] with _nnn_ in the names
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## Invoking STA analysis
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sta_top/toplevel_sta.py <path to verilog> <path to spef> <sdc>
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eg:
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sta_top/toplevel_sta.py ./verilog/gl/user_project_wrapper.v
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./spef/user_project_wrapper.spef ./sta_top/top.sdc > sta.log
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Alternatively you can enter interactive mode after analysis:
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sta_top/toplevel_sta.py ./verilog/gl/user_project_wrapper.v
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./spef/user_project_wrapper.spef ./sta_top/top.sdc -i
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## How it works
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* preprocesses the main Verilog
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* parses the main Verilog to find which modules are used
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* creates a new merged Verilog containing all the module netlists and the main netlist
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* creates a tcl script in the spef directory to load the relevant spefs for each instanced module in the main verilog
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* creates all_sta.tcl in the verilog/gl directory that does the main STA steps (loading design, loading constraints,
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running analyses) - this mimics what OpenLane does
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* creates a script sta.sh in the verilog/gl directory which sets up the environment and invokes STA to run all_sta.tcl
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* runs sta.sh
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## Invoking Spice simulation:
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### Important notes
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* This uses at least ngspice-34, tested on ngspice-39, which has features to increase speed
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and reduce memory image when running with the SkyWater spice models. In addition the following
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needs to be set in ~/spice.rc and/or ~/.spiceinit:
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set ngbehavior=hs
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* Note the spelling of ngbehavior (no u). If this is not set then the simulation will run out of memory]
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* If the critical path changes then the spice_path.py script will need to be adapted to follow suit
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### Instructions
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* go to where the included spice files will be found
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cd $PDK_ROOT/sky130A/libs.tech/ngspice
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* run the script to get the critical path spice circuit - 250 stages of the clock
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<repo directory>/sta_top/spice_path.py path.spice
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* invoke spice (takes about 2 minutes)
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ngspice path.spice
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* run the sim (takes about 2 minutes)
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tran 1n 70n
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* show the results
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plot i0 i250
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This chart shows the input clock and how it changes after 250 blocks. It was simulated for 200n to capture a clean pair of clock pulses.
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