mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 12:46:08 +01:00
Kristaps Jurkans
4afe8f6941
Add new pinouts for SKY130, IHP SG13G2 and GF180mcuD. Valid keys for `show_pinouts` can now be easily seen in the `pinout_map` dictionary: - `caravel` - `openframe` - `openframe_sky130` - `customframe_ihp_sg13g2` - `customframe_gf180mcud` The pinout chapter in the datasheet has also been reworked: the content now exists directly in the typst template instead of being an external file. This is to make use of the `pinout_map` and to allow for easier modification of the content. This change also allows the page to make use of the `callout` function.
405 lines
14 KiB
Typst
405 lines
14 KiB
Typst
#let caravel = {
|
|
align(center,
|
|
table(
|
|
columns: 4,
|
|
align: left,
|
|
table.header(
|
|
[mprj_io_pin], [Function], [Signal], [QFN64 pin]
|
|
),
|
|
|
|
`0`, [Input], [`ui_in[0]`], [`31`],
|
|
`1`, [Input], [`ui_in[1]`], [`32`],
|
|
`2`, [Input], [`ui_in[2]`], [`33`],
|
|
`3`, [Input], [`ui_in[3]`], [`34`],
|
|
`4`, [Input], [`ui_in[4]`], [`35`],
|
|
`5`, [Input], [`ui_in[5]`], [`36`],
|
|
`6`, [Input], [`ui_in[6]`], [`37`],
|
|
`7`, [Analog], [`analog[0]`], [`41`],
|
|
`8`, [Analog], [`analog[1]`], [`42`],
|
|
`9`, [Analog], [`analog[2]`], [`43`],
|
|
`10`, [Analog], [`analog[3]`], [`44`],
|
|
`11`, [Analog], [`analog[4]`], [`45`],
|
|
`12`, [Analog], [`analog[5]`], [`46`],
|
|
`13`, [Input], [`ui_in[7]`], [48],
|
|
`14`, [Input], [`clk` $dagger$], [50],
|
|
`15`, [Input], [`rst_n` $dagger$], [`51`],
|
|
`16`, [Bidirectional], [`uio[0]`], [`53`],
|
|
`17`, [Bidirectional], [`uio[1]`], [`54`],
|
|
`18`, [Bidirectional], [`uio[2]`], [`55`],
|
|
`19`, [Bidirectional], [`uio[3]`], [`57`],
|
|
`20`, [Bidirectional], [`uio[4]`], [`58`],
|
|
`21`, [Bidirectional], [`uio[5]`], [`59`],
|
|
`22`, [Bidirectional], [`uio[6]`], [`60`],
|
|
`23`, [Bidirectional], [`uio[7]`], [`61`],
|
|
`24`, [Output], [`uo_out[0]`], [`62`],
|
|
`25`, [Output], [`uo_out[1]`], [`2`],
|
|
`26`, [Output], [`uo_out[2]`], [`3`],
|
|
`27`, [Output], [`uo_out[3]`], [`4`],
|
|
`28`, [Output], [`uo_out[4]`], [`5`],
|
|
`29`, [Output], [`uo_out[5]`], [`6`],
|
|
`30`, [Output], [`uo_out[6]`], [`7`],
|
|
`31`, [Output], [`uo_out[7]`], [`8`],
|
|
`32`, [Analog], [`analog[6]`], [`11`],
|
|
`33`, [Analog], [`analog[7]`], [`12`],
|
|
`34`, [Analog], [`analog[8]`], [`13`],
|
|
`35`, [Analog], [`analog[9]`], [`14`],
|
|
`36`, [Analog], [`analog[10]`], [`15`],
|
|
`37`, [Analog], [`analog[11]`], [`16`],
|
|
`38`, [Mux Control], [`ctrl_ena`], [`22`],
|
|
`39`, [Mux Control], [`ctrl_sel_inc`], [`24`],
|
|
`40`, [Mux Control], [`ctrl_sel_rst_n`], [`25`],
|
|
`41`, [Reserved], [(none)], [`26`],
|
|
`42`, [Reserved], [(none)], [`27`],
|
|
`43`, [Reserved], [(none)], [`28`],
|
|
)
|
|
)
|
|
|
|
[
|
|
$dagger$ Internally, there's no difference between `clk`, `rst_n` and `ui_in` pins. They are all just bits in the
|
|
`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
|
|
]
|
|
}
|
|
|
|
#let openframe = {
|
|
align(center,
|
|
table(
|
|
columns: 3,
|
|
align: left,
|
|
|
|
table.header(
|
|
[QFN64 Pin], [Function], [Signal]
|
|
),
|
|
|
|
`1`, [Mux Control], [`ctrl_ena`],
|
|
`2`, [Mux Control], [`ctrl_sel_inc`],
|
|
`3`, [Mux Control], [`ctrl_sel_rst_n`],
|
|
`4`, [Reserved], [(none)],
|
|
`5`, [Reserved], [(none)],
|
|
`6`, [Reserved], [(none)],
|
|
`7`, [Reserved], [(none)],
|
|
`8`, [Reserved], [(none)],
|
|
`9`, [Output], [`uo_out[0]`],
|
|
`10`, [Output], [`uo_out[1]`],
|
|
`11`, [Output], [`uo_out[2]`],
|
|
`12`, [Output], [`uo_out[3]`],
|
|
`13`, [Output], [`uo_out[4]`],
|
|
`14`, [Output], [`uo_out[5]`],
|
|
`15`, [Output], [`uo_out[6]`],
|
|
`16`, [Output], [`uo_out[7]`],
|
|
`17`, [Power], [VDD IO],
|
|
`18`, [Ground], [GND IO],
|
|
`19`, [Analog], [`analog[0]`],
|
|
`20`, [Analog], [`analog[1]`],
|
|
`21`, [Analog], [`analog[2]`],
|
|
`22`, [Analog], [`analog[3]`],
|
|
`23`, [Power], [VAA Analog],
|
|
`24`, [Ground], [GND Analog],
|
|
`25`, [Analog], [`analog[4]`],
|
|
`26`, [Analog], [`analog[5]`],
|
|
`27`, [Analog], [`analog[6]`],
|
|
`28`, [Analog], [`analog[7]`],
|
|
`29`, [Ground], [VDD Core],
|
|
`30`, [Power], [VDD Core],
|
|
`31`, [Ground], [GND IO],
|
|
`32`, [Power], [VDD IO],
|
|
`33`, [Bidirectional], [`uio[0]`],
|
|
`34`, [Bidirectional], [`uio[1]`],
|
|
`35`, [Bidirectional], [`uio[2]`],
|
|
`36`, [Bidirectional], [`uio[3]`],
|
|
`37`, [Bidirectional], [`uio[4]`],
|
|
`38`, [Bidirectional], [`uio[5]`],
|
|
`39`, [Bidirectional], [`uio[6]`],
|
|
`40`, [Bidirectional], [`uio[7]`],
|
|
`41`, [Input], [`ui_in[0]`],
|
|
`42`, [Input], [`ui_in[1]`],
|
|
`43`, [Input], [`ui_in[2]`],
|
|
`44`, [Input], [`ui_in[3]`],
|
|
`45`, [Input], [`ui_in[4]`],
|
|
`46`, [Input], [`ui_in[5]`],
|
|
`47`, [Input], [`ui_in[6]`],
|
|
`48`, [Input], [`ui_in[7]`],
|
|
`49`, [Input], [`rst_n` $dagger$],
|
|
`50`, [Input], [`clk` $dagger$],
|
|
`51`, [Ground], [GND IO],
|
|
`52`, [Power], [VDD IO],
|
|
`53`, [Analog], [`analog[8]`],
|
|
`54`, [Analog], [`analog[9]`],
|
|
`55`, [Analog], [`analog[10]`],
|
|
`56`, [Analog], [`analog[11]`],
|
|
`57`, [Ground], [GND Analog],
|
|
`58`, [Power], [VDD Analog],
|
|
`59`, [Analog], [`analog[12]`],
|
|
`60`, [Analog], [`analog[13]`],
|
|
`61`, [Analog], [`analog[14]`],
|
|
`62`, [Analog], [`analog[15]`],
|
|
`63`, [Ground], [GND Core],
|
|
`64`, [Power], [VDD Core]
|
|
)
|
|
)
|
|
|
|
[
|
|
$dagger$ Internally, there's no difference between `clk`, `rst_n` and `ui_in` pins. They are all just bits in the
|
|
`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
|
|
]
|
|
}
|
|
|
|
#let openframe_sky130 = {
|
|
align(center,
|
|
table(
|
|
columns: 4,
|
|
align: left,
|
|
|
|
table.header(
|
|
[QFN64 pin], [mprj_io_pin], [Function], [Signal]
|
|
),
|
|
|
|
`1`, `vssa2`, [Ground], [GND],
|
|
`2`, `25`, [Output], `uo[1]`,
|
|
`3`, `26`, [Output], `uo[2]`,
|
|
`4`, `27`, [Output], `uo[3]`,
|
|
`5`, `28`, [Output], `uo[4]`,
|
|
`6`, `29`, [Output], `uo[5]`,
|
|
`7`, `30`, [Output], `uo[6]`,
|
|
`8`, `31`, [Output], `uo[7]`,
|
|
`9`, `vdda2`, [Power], [VDD Analog],
|
|
`10`, `vssd2`, [Ground], [GND],
|
|
`11`, `32`, [Analog], `analog[6]`,
|
|
`12`, `33`, [Analog], `analog[7]`,
|
|
`13`, `34`, [Analog], `analog[8]`,
|
|
`14`, `35`, [Analog], `analog[9]`,
|
|
`15`, `36`, [Analog], `analog[10]`,
|
|
`16`, `37`, [Analog], `analog[11]`,
|
|
`17`, `vddio`, [Power], [VDD IO],
|
|
`18`, `vccd`, [Power], [VDD Core],
|
|
`19`, `NC`, [], [],
|
|
`20`, `vssa`, [Ground], [GND],
|
|
`21`, `resetb`, [], [],
|
|
`22`, `38`, [Mux], `ctrl_ena`,
|
|
`23`, `vssd`, [Ground], [GND],
|
|
`24`, `39`, [Mux], `ctrl_sel_inc`,
|
|
`25`, `40`, [Mux], `ctrl_sel_rst_n`,
|
|
`26`, `41`, [Reserved], [(none)],
|
|
`27`, `42`, [Reserved], [(none)],
|
|
`28`, `43`, [Reserved], [(none)],
|
|
`29`, `vssio`, [Ground], [GND],
|
|
`30`, `vdda`, [Power], [VDD Analog],
|
|
`31`, `0`, [Input], `ui[0]`,
|
|
`32`, `1`, [Input], `ui[1]`,
|
|
`33`, `2`, [Input], `ui[2]`,
|
|
`34`, `3`, [Input], `ui[3]`,
|
|
`35`, `4`, [Input], `ui[4]`,
|
|
`36`, `5`, [Input], `ui[5]`,
|
|
`37`, `6`, [Input], `ui[6]`,
|
|
`38`, `vssa1`, [Ground], [GND],
|
|
`39`, `vssd1`, [Ground], [GND],
|
|
`40`, `vdda1`, [Power], [VDD Analog],
|
|
`41`, `7`, [Analog], `analog[0]`,
|
|
`42`, `8`, [Analog], `analog[1]`,
|
|
`43`, `9`, [Analog], `analog[2]`,
|
|
`44`, `10`, [Analog], `analog[3]`,
|
|
`45`, `11`, [Analog], `analog[4]`,
|
|
`46`, `12`, [Analog], `analog[5]`,
|
|
`47`, `vdda1`, [Power], [VDD Analog],
|
|
`48`, `13`, [Input], `ui[7]`,
|
|
`49`, `vccd1`, [Power], [VDD Core],
|
|
`50`, `14`, [Input], [`u_clk` $dagger$],
|
|
`51`, `15`, [Input], [`u_rst_n` $dagger$],
|
|
`52`, `vssa1`, [Ground], [GND],
|
|
`53`, `16`, [Bidirectional], `io[0]`,
|
|
`54`, `17`, [Bidirectional], `io[1]`,
|
|
`55`, `18`, [Bidirectional], `io[2]`,
|
|
`56`, `vssio`, [Ground], [GND],
|
|
`57`, `19`, [Bidirectional], `io[3]`,
|
|
`58`, `20`, [Bidirectional], `io[4]`,
|
|
`59`, `21`, [Bidirectional], `io[5]`,
|
|
`60`, `22`, [Bidirectional], `io[6]`,
|
|
`61`, `23`, [Bidirectional], `io[7]`,
|
|
`62`, `24`, [Output], `uo[0]`,
|
|
`63`, `vccd2`, [Power], [VDD Core],
|
|
`64`, `vddio`, [Power], [VDD IO],
|
|
`EPAD`, [], [Ground], []
|
|
)
|
|
)
|
|
|
|
[
|
|
$dagger$ Internally, there's no difference between `u_clk`, `u_rst_n`, and `ui` pins. They are all just bits in the
|
|
`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
|
|
]
|
|
}
|
|
|
|
#let customframe_ihp_sg13g2 = {
|
|
align(center,
|
|
table(
|
|
columns: 4,
|
|
align: left,
|
|
|
|
table.header(
|
|
[Die Pad], [QFN64 pin], [Function], [Signal]
|
|
),
|
|
|
|
`0`, `1`, [Mux Control], `ctrl_ena`,
|
|
`1`, `2`, [Mux Control], `ctrl_sel_inc`,
|
|
`2`, `3`, [Mux Control], `ctrl_sel_rst_n`,
|
|
`3`, `4`, [Reserved], [],
|
|
`4`, `5`, [Reserved], [],
|
|
`5`, `6`, [Reserved], [],
|
|
`6`, `7`, [Reserved], [],
|
|
`7`, `8`, [Reserved], [],
|
|
`8`, `9`, [Output], `uo[0]`,
|
|
`9`, `10`, [Output], `uo[1]`,
|
|
`10`, `11`, [Output], `uo[2]`,
|
|
`11`, `12`, [Output], `uo[3]`,
|
|
`12`, `13`, [Output], `uo[4]`,
|
|
`13`, `14`, [Output], `uo[5]`,
|
|
`14`, `15`, [Output], `uo[6]`,
|
|
`15`, `16`, [Output], `uo[7]`,
|
|
`16`, `17`, [Power], [VDD IO],
|
|
`17`, `18`, [Ground], [GND IO],
|
|
`18`, `19`, [Analog], `analog[0]`,
|
|
`19`, `20`, [Analog], `analog[1]`,
|
|
`20`, `21`, [Analog], `analog[2]`,
|
|
`21`, `22`, [Analog], `analog[3]`,
|
|
`22`, `23`, [Power], [VDD Analog],
|
|
`23`, `24`, [Ground], [GND Analog],
|
|
`24`, `25`, [Analog], `analog[4]`,
|
|
`25`, `26`, [Analog], `analog[5]`,
|
|
`26`, `27`, [Analog], `analog[6]`,
|
|
`27`, `28`, [Analog], `analog[7]`,
|
|
`28`, `29`, [Ground], [GND Core],
|
|
`29`, `30`, [Power], [VDD Core],
|
|
`30`, `31`, [Ground], [GND IO],
|
|
`31`, `32`, [Power], [VDD IO],
|
|
`32`, `33`, [Bidirectional], `uio[0]`,
|
|
`33`, `34`, [Bidirectional], `uio[1]`,
|
|
`34`, `35`, [Bidirectional], `uio[2]`,
|
|
`35`, `36`, [Bidirectional], `uio[3]`,
|
|
`36`, `37`, [Bidirectional], `uio[4]`,
|
|
`37`, `38`, [Bidirectional], `uio[5]`,
|
|
`38`, `39`, [Bidirectional], `uio[6]`,
|
|
`39`, `40`, [Bidirectional], `uio[7]`,
|
|
`40`, `41`, [Input], `ui[0]`,
|
|
`41`, `42`, [Input], `ui[1]`,
|
|
`42`, `43`, [Input], `ui[2]`,
|
|
`43`, `44`, [Input], `ui[3]`,
|
|
`44`, `45`, [Input], `ui[4]`,
|
|
`45`, `46`, [Input], `ui[5]`,
|
|
`46`, `47`, [Input], `ui[6]`,
|
|
`47`, `48`, [Input], `ui[7]`,
|
|
`48`, `49`, [Input], [`u_rst_n` $dagger$],
|
|
`49`, `50`, [Input], [`u_clk` $dagger$],
|
|
`50`, `51`, [Ground], [GND IO],
|
|
`51`, `52`, [Power], [VDD IO],
|
|
`52`, `53`, [Analog], `analog[8]`,
|
|
`53`, `54`, [Analog], `analog[9]`,
|
|
`54`, `55`, [Analog], `analog[10]`,
|
|
`55`, `56`, [Analog], `analog[11]`,
|
|
`56`, `57`, [Ground], [GND Analog],
|
|
`57`, `58`, [Power], [VDD Analog],
|
|
`58`, `59`, [Analog], `analog[12]`,
|
|
`59`, `60`, [Analog], `analog[13]`,
|
|
`60`, `61`, [Analog], `analog[14]`,
|
|
`61`, `62`, [Analog], `analog[15]`,
|
|
`62`, `63`, [Ground], [GND Core],
|
|
`63`, `64`, [Power], [VDD Core],
|
|
`SUB`, `EPAD`, [Ground], [],
|
|
)
|
|
)
|
|
|
|
[
|
|
$dagger$ Internally, there's no difference between `u_clk`, `u_rst_n`, and `ui` pins. They are all just bits in the
|
|
`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
|
|
]
|
|
}
|
|
|
|
#let customframe_gf180mcud = {
|
|
align(center,
|
|
table(
|
|
columns: 4,
|
|
align: left,
|
|
|
|
table.header(
|
|
[Die Pad], [QFN64 pin], [Function], [Signal]
|
|
),
|
|
|
|
`0`, `1`, [Mux Control], `ctrl_ena`,
|
|
`1`, `2`, [Mux Control], `ctrl_sel_inc`,
|
|
`2`, `3`, [Mux Control], `ctrl_sel_rst_n`,
|
|
`3`, `4`, [Reserved], [],
|
|
`4`, `5`, [Reserved], [],
|
|
`5`, `6`, [Reserved], [],
|
|
`6`, `7`, [Reserved], [],
|
|
`7`, `8`, [Reserved], [],
|
|
`8`, `EPAD`, [Ground], [GND IO],
|
|
`9`, `9`, [Output], `uo[0]`,
|
|
`10`, `10`, [Output], `uo[1]`,
|
|
`11`, `11`, [Output], `uo[2]`,
|
|
`12`, `12`, [Output], `uo[3]`,
|
|
`13`, `13`, [Output], `uo[4]`,
|
|
`14`, `14`, [Output], `uo[5]`,
|
|
`15`, `15`, [Output], `uo[6]`,
|
|
`16`, `16`, [Output], `uo[7]`,
|
|
`17`, `17`, [Power], [VDD IO],
|
|
`18`, `EPAD`, [Ground], [GND IO],
|
|
`19`, `18`, [Analog], `analog[0]`,
|
|
`20`, `19`, [Analog], `analog[1]`,
|
|
`21`, `20`, [Analog], `analog[2]`,
|
|
`22`, `21`, [Analog], `analog[3]`,
|
|
`23`, `22`, [Analog], `analog[4]`,
|
|
`24`, `23`, [Analog], `analog[5]`,
|
|
`25`, `24`, [Power], [PWR Analog],
|
|
`26`, `EPAD`, [Ground], [GND Analog],
|
|
`27`, `25`, [Analog], `analog[6]`,
|
|
`28`, `26`, [Analog], `analog[7]`,
|
|
`29`, `27`, [Analog], `analog[8]`,
|
|
`30`, `28`, [Analog], `analog[9]`,
|
|
`31`, `29`, [Analog], `analog[10]`,
|
|
`32`, `30`, [Analog], `analog[11]`,
|
|
`33`, `EPAD`, [Ground], [GND Core],
|
|
`34`, `31`, [Power], [VDD Core],
|
|
`35`, `EPAD`, [Ground], [GND IO],
|
|
`36`, `32`, [Power], [VDD IO],
|
|
`37`, `33`, [Bidirectional], `uio[0]`,
|
|
`38`, `34`, [Bidirectional], `uio[1]`,
|
|
`39`, `35`, [Bidirectional], `uio[2]`,
|
|
`40`, `36`, [Bidirectional], `uio[3]`,
|
|
`41`, `37`, [Bidirectional], `uio[4]`,
|
|
`42`, `38`, [Bidirectional], `uio[5]`,
|
|
`43`, `39`, [Bidirectional], `uio[6]`,
|
|
`44`, `40`, [Bidirectional], `uio[7]`,
|
|
`45`, `EPAD`, [Ground], [GND IO],
|
|
`46`, `41`, [Input], `ui[0]`,
|
|
`47`, `42`, [Input], `ui[1]`,
|
|
`48`, `43`, [Input], `ui[2]`,
|
|
`49`, `44`, [Input], `ui[3]`,
|
|
`50`, `45`, [Input], `ui[4]`,
|
|
`51`, `46`, [Input], `ui[5]`,
|
|
`52`, `47`, [Input], `ui[6]`,
|
|
`53`, `48`, [Input], `ui[7]`,
|
|
`54`, `49`, [Input], [`u_rst_n` $dagger$],
|
|
`55`, `50`, [Input], [`u_clk` $dagger$],
|
|
`56`, `EPAD`, [Ground], [GND IO],
|
|
`57`, `51`, [Power], [VDD IO],
|
|
`58`, `52`, [Analog], `analog[12]`,
|
|
`59`, `53`, [Analog], `analog[13]`,
|
|
`60`, `54`, [Analog], `analog[14]`,
|
|
`61`, `55`, [Analog], `analog[15]`,
|
|
`62`, `EPAD`, [Ground], [GND Analog],
|
|
`63`, `56`, [Power], [PWR Analog],
|
|
`64`, `57`, [Analog], `analog[16]`,
|
|
`65`, `58`, [Analog], `analog[17]`,
|
|
`66`, `59`, [Analog], `analog[18]`,
|
|
`67`, `60`, [Analog], `analog[19]`,
|
|
`68`, `61`, [Analog], `analog[20]`,
|
|
`69`, `62`, [Analog], `analog[21]`,
|
|
`70`, `EPAD`, [Ground], [GND Core],
|
|
`71`, `63`, [Power], [VDD Core],
|
|
`72`, `EPAD`, [Ground], [GND IO],
|
|
`73`, `64`, [Power], [VDD IO]
|
|
)
|
|
)
|
|
|
|
[
|
|
$dagger$ Internally, there's no difference between `u_clk`, `u_rst_n`, and `ui` pins. They are all just bits in the
|
|
`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
|
|
]
|
|
} |