fix(tt_tool): always specify the power pin names

Up to this point, we relied on the PDK's default power pin names. However, the defaults names for GF180, VDD and VSS, are not compatible with Tiny Tapeout, which expects VPWR (or VDPWR) and VGND. So instead, we set the VDD_PIN and GND_PIN config options explicitly.

project.py

@@ -488,6 +488,8 @@ class Project:
             "VERILOG_FILES": [f"dir::{src}" for src in self.sources],
             "DIE_AREA": die_area,
             "FP_DEF_TEMPLATE": def_template,
+            "VDD_PIN": "VPWR",
+            "GND_PIN": "VGND",
             "RT_MAX_LAYER": self.tech.project_top_metal_layer,
         }
         write_config(config, os.path.join(self.src_dir, "user_config"), ("json",))