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fix(tt_tool): always specify the power pin names

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Up to this point, we relied on the PDK's default power pin names. However, the defaults names for GF180, VDD and VSS, are not compatible with Tiny Tapeout, which expects VPWR (or VDPWR) and VGND. So instead, we set the VDD_PIN and GND_PIN config options explicitly.
This commit is contained in:
Uri Shaked
2025-09-29 16:17:23 +03:00
parent 1ab2abc8d5
commit fcf7e8a37f
1 changed files with 2 additions and 0 deletions
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project.py
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@@ -488,6 +488,8 @@ class Project:
"VERILOG_FILES": [f"dir::{src}" for src in self.sources], "VERILOG_FILES": [f"dir::{src}" for src in self.sources],
"DIE_AREA": die_area, "DIE_AREA": die_area,
"FP_DEF_TEMPLATE": def_template, "FP_DEF_TEMPLATE": def_template,
"VDD_PIN": "VPWR",
"GND_PIN": "VGND",
"RT_MAX_LAYER": self.tech.project_top_metal_layer, "RT_MAX_LAYER": self.tech.project_top_metal_layer,
} }
write_config(config, os.path.join(self.src_dir, "user_config"), ("json",)) write_config(config, os.path.join(self.src_dir, "user_config"), ("json",))