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Author SHA1 Message Date
Uri Shaked 7732914248 fix(tech/sky130A): remove ROW and TRACK lines from .def files 
LibreLane runs happily without them, but they cause issue when using a different standard cell library (e.g. hs instead of the default hd).
 2025-09-24 22:36:24 +03:00
Uri Shaked c4892189f9 chore: upgrade cocotb, pytest 2025-09-23 16:38:27 +03:00
Uri Shaked 305f3ecaf8 fix(tt_tool): vary RT_MAX_LAYER per tech 
Each tech has a different metal stackup, so user projects get a different top routing metal layer. tt-support-tools now handles this instead of the user having to worry about this when switching PDKs.
 2025-09-18 11:45:44 +03:00
Uri Shaked 84efb79dd7 feat(tt_tool): --create-tt-submission command 2025-09-18 11:36:03 +03:00
Uri Shaked ae0894906a Merge pull request #115 from TinyTapeout/tech-refactor 
Refactor to separate PDK/tech-specific code
 2025-09-14 14:51:28 +03:00
Uri Shaked 0529b699de fix(precheck): rename "sky130" to "sky130A" 
Keep the tech naming consistent with the rest of tt-support-tools code
 2025-09-13 20:28:54 +03:00
Uri Shaked 498e098f9a refactor(rom): unified librelane config with per-PDK overrides 2025-09-13 20:28:54 +03:00
Uri Shaked 28fd25f684 refactor: separate tech specific code 
Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
 2025-09-13 20:28:48 +03:00
Uri Shaked c67d54ee54 fix(tt_tool): routing stats broken for LibreLane 3.x 2025-09-09 16:14:57 +03:00
Uri Shaked dc0f9c87b4 ci(test-harden): GH action that tests GDS hardening 2025-09-09 16:14:27 +03:00
Uri Shaked 4347c961d0 refactor(tt_tool): openlane2 -> librelane 2025-09-08 17:51:13 +03:00
Uri Shaked 5e9fff900e cleanup: remove legacy code 2025-09-08 16:02:33 +03:00
Uri Shaked 278718ca12 chore: update efabless -> chipfoundry 2025-09-08 15:44:33 +03:00
Uri Shaked 9788d3d545 fix(rom): use DECAP_CELL settings from PDK 2025-09-08 15:44:32 +03:00
Uri Shaked 9024d9ff0e fix(rom): extend 7-segment alphabet 
Add "c", "a", "d" and "s", "k", "y" to the 7-segment encoding dictionary, make "H" and "I" uppercase (so IHP is rendered uppercase and not lowercase)
 2025-09-08 15:44:27 +03:00
Uri Shaked ef2b0de84b fix(configure): fails due to missing args.pdk 
slightly refactor project.py to make the code more extensible to future PDK support
 2025-09-02 17:42:28 +03:00
Uri Shaked 9519fa87fd fix(tt_tool): project tile configuration always checked against SKY130 tile sizes 2025-09-02 17:20:02 +03:00
Uri Shaked 9a59843db0 style(fpga): python code formatting issues 2025-09-02 17:11:26 +03:00
Uri Shaked a95630a378 feat(ihp): add 6x4 template 2025-09-02 17:07:57 +03:00
Uri Shaked 68e2a49925 feat(logo): corner logo for IHP 2025-08-20 10:48:28 +03:00
Uri Shaked 58807a2145 feat(logo): IHP shuttle support 2025-08-19 23:14:09 +03:00
Uri Shaked d69a0eac0c fix(logo): support to longer shuttle names (e.g. TTCAD25a) 2025-08-19 23:13:26 +03:00
Uri Shaked 2675235ea2 fix(shuttle): don't copy pg macros when copying final results 
There is no real reason to copy them, and they vary per shuttle type
 2025-08-19 22:14:41 +03:00
Uri Shaked bafe03504f feat(shuttle): ihp power switch support 2025-08-19 16:26:05 +03:00
Uri Shaked 10e2f1108c feat(shuttle): report missing muxes 
When we have x4-tile high projects, some muxes will be missing. Report them as such in the shuttle index, so that the shuttle map on the website displays correctly.
 2025-08-15 20:12:32 +03:00
Uri Shaked 62f5e45102 fix: mistune type errors 2025-08-15 20:12:27 +03:00
Uri Shaked bebe93d93b fix(precheck): add HeatRes.drawing to list of valid IHP SG13G2 layers 2025-05-09 22:26:37 +03:00
Uri Shaked 0baf1ece4b feat(precheck): IHP KLayout DRC 2025-04-16 17:56:01 +03:00
Uri Shaked fe543406d6 fix(precheck): disable power pin check for IHP 
IHP provided verilog models do not have power ports, so we don't use powered netlists, and thus no need to check for power pins in the GL verilog.
 2025-04-16 17:12:34 +03:00
Uri Shaked 746789020e fix(precheck): update valid list of IHP SG13G2 layers 
List given by @smunaut
 2025-04-16 16:58:45 +03:00
Uri Shaked c350c2ed16 feat(precheck): initial IHP support 
still missing the IHP Klayout DRC deck
 2025-04-16 08:28:51 +03:00
Uri Shaked 49b57ea0bb fix: TinyTapeout -> Tiny Tapeout 2025-04-14 09:40:58 +03:00
Uri Shaked f3b7f15acd docs: update credits for ihp shuttles 2025-03-31 19:20:35 +03:00
Uri Shaked 6bb8082f65 cleanup(rom): remove old build script 2025-03-30 12:56:39 +03:00
Uri Shaked 0985eb1d46 feat(rom): support for reading sequentially 
This helps in case where some of the `ui_in` pins can't be set due to a plugged-in Pmod or other conflicting driver.
 2025-02-02 11:13:48 +02:00
Uri Shaked 8f2ff888d6 style(rom): format verilog code with verible 2025-02-02 10:48:37 +02:00
Uri Shaked a48b1c7446 feat(configure): support for brotli-compressed GDS files 
Recently, we started compressing GDS files larger than 25 MB due to GitHub REST API blob size limitations.
 2024-11-05 14:56:53 +02:00
Uri Shaked b176ed7ced feat(orfs): allow overriding PDN config 2024-10-25 10:02:14 +03:00
Uri Shaked 05f4c62dc1 feat(configure): add no_power_gating configuration 
When set, it configures all user projects with `pg_vdd: false`. This is for ihp0p2 shuttle, which doesn't have power gating yet (tt-multiplexer defaults to enable the pg when `pg_vdd` is not explicitly specified).
 2024-10-22 11:50:26 +03:00
Uri Shaked d1e8e31569 feat(configure): add --create-ihp-submission command 
similar to create-efabless-submission, but uses the ihp directory and skips copying user_defines.v
 2024-10-21 21:53:54 +03:00
Uri Shaked f3e3861176 fix(shuttle): missing powered GL netlists for IHP 
Hardening requires powered netlists, GL required unpowered netlists. So now we keep both.
 2024-10-21 16:53:14 +03:00
Uri Shaked 4eb37893cb fix(configure): fails on ihp user submissions 
IHP submissions do not have powered netlists, so add a flag to specify that in the shuttles config.yaml file.
 2024-10-21 16:01:33 +03:00
Uri Shaked 9dc2af14c8 feat(configure): make top_level_macro configurable 
For IHP shuttles, we need "tt_ihp_wrapper" instead of "openframe_project_wrapper"
 2024-10-21 13:31:51 +03:00
Uri Shaked cbbf76df98 feat(rom): ihp hardening support 2024-10-21 10:09:05 +03:00
Uri Shaked 474b576b3e fix(rom): fails to build on ihp shuttles 
Add "i", "h", "p" to the 7-segment encoding dictionary.
 2024-10-20 23:44:55 +03:00
Uri Shaked 07e91d894b chore: upgrade cocotb to 1.9.1 #69 
cocotb==1.8.1 fails building on macOS ARM-based systems. More recent versions build successfully.

resolves #69
 2024-09-27 12:19:45 +03:00
Uri Shaked 96f3577cad chore(precheck): update klayout DRC deck 
following efabless/mpw_precheck#289
 2024-09-11 23:39:59 +03:00
Uri Shaked 4b04660726 fix(reharden): support new shuttle index format (v3) 2024-09-09 23:19:15 +03:00
Uri Shaked 587b6cb0d0 fix: type error 2024-08-30 11:44:13 +03:00
Uri Shaked d3ed62bc00 fix(configure): support declaring power ports as inout 
OpenLane 2.1.1 produces a verilog netlist with the power ports declared as "inout", where as 2.0.8 and earlier declared the power ports as "input". Change our scripts to accept "inout" as a valid direction for the power ports.
 2024-08-30 11:39:52 +03:00
Uri Shaked 3c88e6eb04 cleanup(website): remove hugo related functionality 
Project pages are now dynamically generated based on the shuttle index.
 2024-07-16 15:15:09 +03:00
Uri Shaked 63eb3d550f feat(configure): copy tt_pg_1v8_4 macro 2024-07-04 22:17:53 +03:00
Uri Shaked 054e41b839 feat(configure): set "pg_vaa" in modules.yaml for 3v3 projects 
This property tells the mux to include 3v3 power gate (in addition to the standard 1v8 power gate)
 2024-07-04 21:38:40 +03:00
Uri Shaked 3c25ae08a6 feat(analog): magic script to create a new analog project 2024-06-26 21:22:52 +03:00
Uri Shaked 674fdc7ef7 fix(precheck): update analog template paths 2024-06-18 14:29:40 +03:00
Uri Shaked ada2e9215e feat(def): update analog templates for tt08 2024-06-18 14:25:27 +03:00
Uri Shaked e64b30fcb3 feat(def): 3x4, 4x4 and 5x4 tile sizes 2024-06-10 12:14:40 +03:00
Uri Shaked a4a87edf2a feat(configure): copy new tt08 power gate macros 
tt_pg_1v8_1, tt_pg_1v8_2, and tt_pg_3v3_2
 2024-06-09 16:11:30 +03:00
Uri Shaked 3d87be1a9c feat(def): update tt_block def files for tt08 
The pin positions have changed to keep space for the analog supply voltage gating transistor
 2024-06-09 08:42:59 +03:00
Uri Shaked 6924b7464b fix: hardening fails with openlane v2024.05.28 
/bin/bash is no longer present in the container image, so we had to remove it from the docker command line
 2024-06-02 10:22:53 +03:00
Uri Shaked c7cd708524 fix: remove support for openlane yaml config 
see https://github.com/TinyTapeout/tt-support-tools/pull/55#issuecomment-2138626540 for reasoning
 2024-06-01 17:25:23 +03:00
Uri Shaked 11b2d371b4 fix(documentation): exit with error code if PDF generation fails 2024-05-29 17:02:39 +03:00
Uri Shaked 17e08942b2 feat(rom): add Magic and CRC32 fields 2024-05-29 16:18:08 +03:00
Uri Shaked bcf20bea0b fix(datasheet): broken datasheet 
it broke after the fix from 74796c81c7
 2024-05-29 15:55:39 +03:00
Uri Shaked 74796c81c7 fix: analog designs always get 6 pins connected 
instead, we should read the `analog_pins` setting from the project's info.yaml
 2024-05-29 13:19:29 +03:00
Uri Shaked 8e2da84a18 feat: python 3.12 support #53 
close #53
 2024-05-20 10:36:19 +03:00
Uri Shaked d2d27ab36c fix(precheck): fails on projects in shuttle repository 
It can't find info.yaml, since it's looking for it in the parent directory of the gds while info.yaml is in the same directory as the gds.
 2024-05-07 09:01:09 +03:00
Uri Shaked 79f41ef2e1 fix(datasheet): shuttle id missing in hugo content index 
We generate {shuttle_id} instead of actually putting the shuttle id there, causing the shuttle map not to appear.
 2024-05-07 08:47:00 +03:00
Uri Shaked af1f250dba fix(datasheet): broken full gds render / chip map 2024-05-07 00:24:55 +03:00
Uri Shaked 0c171af9b4 feat(fpga): read seed / target frequency from environment 
Read the values from TT_FPGA_SEED / TT_FPGA_FREQ, and default to 12 MHz frequency.
 2024-05-01 23:47:35 +03:00
Uri Shaked b6ec741349 feat(fpga): initial implementation 
Adds a new `tt_tool.py --create-fpga-bitstream` flag that creates a TT Sim FPGA bitstream from the user's project.
 2024-05-01 23:13:21 +03:00
Uri Shaked 81bffaf9d6 fix(datasheet): update website index header for TT07 2024-05-01 01:25:21 +03:00
Uri Shaked 51e5747c09 fix(tt_tool): analog project can have up to 6 analog pins 2024-04-27 22:30:43 +03:00
Uri Shaked 60c8ff8b8e fix(configure): update synth stats paths for tt06 2024-04-26 12:23:38 +03:00
Uri Shaked 4b2bb6d000 feat(precheck): verify top level macro name 
This issue appeared in tt06, in the following analog project: https://github.com/davidparent/tt_resistor_test/tree/fdc74c92ec0ec2b9817f0ea6823daa62f8ca5401/
 2024-04-23 22:57:52 +03:00
Uri Shaked 793d01ab13 feat(tt_tool): improve "pinout" section validation 
- Verify that the user filled the pinout (at least one pin description)
- Disallow unrecognized keys
 2024-04-23 00:10:44 +03:00
Uri Shaked 730fb02726 fix(website): images missing from website 
TinyTapeout/tinytapeout_www#84
 2024-04-22 00:12:20 +03:00
Uri Shaked a6d2dae7aa fix(precheck): remove unused --markdown-report arg 
the markdown report is always generated anyway
 2024-04-21 00:18:35 +03:00
Uri Shaked 3067026096 feat(precheck): add prBoundary check 
verifies that prBoundary layer exists
 2024-04-21 00:17:48 +03:00
Uri Shaked ef33610c61 feat: update analog templates for tt07 
make the analog pins wider - 0.9um instead of 0.6 um
 2024-04-20 13:39:53 +03:00
Uri Shaked 1f66d890ef fix(configure): project loading broken 2024-04-20 01:06:04 +03:00
Uri Shaked f8dc00aeac feat(precheck): add zeroarea check 2024-04-20 00:36:09 +03:00
Uri Shaked bd22f82b1b fix(configure): unhappy types 2024-04-20 00:26:49 +03:00
Uri Shaked 7f56a586c0 feat(configure): support for loading only a subset of the projects 
specified by the `TT_ONLY_PROJECTS` environment variable, e.g.:

```bash
TT_ONLY_PROJECTS="tt_um_chip_rom,tt_um_factory_test"
```
 2024-04-19 17:39:16 +03:00
Uri Shaked c74b14ac00 fix(datasheet): don't escape latex in user docs (info.md) 2024-04-17 21:28:47 +03:00
Uri Shaked eed8309348 chore(precheck): update klayout DRC rules 
following efabless/mpw_precheck#271
 2024-04-16 22:39:54 +03:00
Uri Shaked d5153c3f22 fix(tt_tool): clock issue warnings break with custom openlane configs 
they break when some of the steps are disabled, e.g. https://github.com/iic-jku/jku-tt06-tdc-v2/
 2024-04-13 20:31:27 +02:00
Uri Shaked d9a6d6206d fix(datasheet): broken images 2024-04-11 15:14:31 +03:00
Uri Shaked 9c7ebcb731 feat(tt_tool): display clock issue warnings #34 2024-04-08 15:10:47 +03:00
Uri Shaked 16fb26f5e6 fix(datasheet): images missing #32 2024-04-08 15:04:28 +03:00
Uri Shaked 1ebe1ef29b fix(configure): correct project type in shuttle_index.md for analog projects 
was "HDL", should be "Analog"
 2024-04-06 14:51:48 +03:00
Uri Shaked ef272636b7 ci(test-precheck): update action dependencies 2024-04-05 11:50:00 +03:00
Uri Shaked b544d27db7 fix(precheck): bump klayout dependency 
See KLayout/klayout#1670 for details
 2024-04-01 21:43:25 +03:00
Uri Shaked 11a1c442ee feat(precheck): pin_label_purposes_overlapping_drawing check 2024-03-31 21:20:37 +03:00
Uri Shaked ca190609c6 fix: pass yosys commands through an environment variable 
should be safer than passing them on shell commandline
 2024-03-30 01:32:08 +03:00
Uri Shaked 1e052887a2 fix: yowasp-yosys chokes on complex verilog modules 
reproduces with https://github.com/Lucaz97/tt06_RNG2

as a workaround, we first try to read the first verilog source file, and only if we can't find the top level verilog module there, we read the rest of the files.
 2024-03-30 01:12:06 +03:00
Uri Shaked e3fac0ab40 feat: "layout" section in shuttle_index 
contains information about the type each each mux (analog / digital)
 2024-03-21 23:36:50 +02:00
Uri Shaked a97e6b03b6 feat(configure): copy analog switch (asw) macro 2024-03-21 18:09:32 +02:00
Uri Shaked 316141d73a fix(ci): mypy check fails 
upgrade python from 3.9 to 3.11
 2024-03-19 11:47:36 +02:00
Uri Shaked ef5539b7a0 feat: new format for shuttle_index 
1. Bump "version" to 3
2. Rename "shuttle" to "name"
2. Rename "mux" to "projects", and turn it from a dict into a list
3. Project entries: add "address" (which was previously the key of the "mux" dict), remove "features" and add optional "analog_pins" with a list of analog pin assignment.
 2024-03-18 01:16:22 +02:00