Uri Shaked
9056f14ddc
feat(tt_tool): set TT_PDK in user project OAS file
...
The TT_PDK property will be set to the PDK used to harden the project
2025-09-25 09:42:07 +03:00
Uri Shaked
305f3ecaf8
fix(tt_tool): vary RT_MAX_LAYER per tech
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Each tech has a different metal stackup, so user projects get a different top routing metal layer. tt-support-tools now handles this instead of the user having to worry about this when switching PDKs.
2025-09-18 11:45:44 +03:00
Uri Shaked
84efb79dd7
feat(tt_tool): --create-tt-submission command
2025-09-18 11:36:03 +03:00
Uri Shaked
28fd25f684
refactor: separate tech specific code
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Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
2025-09-13 20:28:48 +03:00
Uri Shaked
c67d54ee54
fix(tt_tool): routing stats broken for LibreLane 3.x
2025-09-09 16:14:57 +03:00
Uri Shaked
4347c961d0
refactor(tt_tool): openlane2 -> librelane
2025-09-08 17:51:13 +03:00
Uri Shaked
ef2b0de84b
fix(configure): fails due to missing args.pdk
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slightly refactor project.py to make the code more extensible to future PDK support
2025-09-02 17:42:28 +03:00
Uri Shaked
9519fa87fd
fix(tt_tool): project tile configuration always checked against SKY130 tile sizes
2025-09-02 17:20:02 +03:00
Uri Shaked
9a59843db0
style(fpga): python code formatting issues
2025-09-02 17:11:26 +03:00
Pat Deegan
41d52a230e
TT06+ asic sim support, prelim
2025-08-25 16:24:29 -04:00
htfab
7d341a1195
feat: add support for IHP PDK with OpenLane2 (for user projects)
2025-03-06 08:10:24 +02:00
htfab
b9e2e9fc08
feat(docs): use github-flavored markdown at the shuttle level too
2025-01-06 06:59:58 +02:00
htfab
d89635e143
feat!: drop openlane1 support
2024-12-18 09:02:55 +02:00
htfab
525e0a5e1a
feat(docs): parse info.md as github-flavored markdown
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resolves #78
2024-12-05 02:41:50 +01:00
Uri Shaked
b176ed7ced
feat(orfs): allow overriding PDN config
2024-10-25 10:02:14 +03:00
htfab
0c16b17395
fix(orfs): link to the 1.2V version of the cell library pdf from the summary
2024-10-21 19:23:23 +03:00
htfab
6fbbea4bce
fix(orfs): fail if violations remain after detailed routing
2024-10-21 14:20:32 +03:00
htfab and htfab
74edb57680
fix(orfs): use our fork of the IHP PDK ( #73 )
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* fix(orfs): remove special handling of DRC error Pin.f.M5
* fix(orfs): remove patch for IHP PDK
We use our own fork now with the patch integrated.
* fix(orfs): allow updating ORFS platform files from IHP PDK
---------
Co-authored-by: htfab <mpw@htamas.net >
2024-10-20 08:11:56 +03:00
htfab and htfab
dcab9fc353
feat: add DRC & LVS for ORFS ( #72 )
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Co-authored-by: htfab <mpw@htamas.net >
2024-10-14 15:04:43 +03:00
htfab
30dbb0cd1b
feat: merge VHDL support branch
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os.makedirs() line contributed by @gfcwfzkm
2024-09-30 18:19:46 +03:00
htfab
d862b7845c
feat: change run tag from ihp to wokwi
2024-09-24 23:01:57 +03:00
htfab
f8cc66a644
feat: add experimental IHP support
2024-09-24 22:23:12 +03:00
htfab
dd77f85278
fix: handle PDK_ROOT being unset for volare
2024-09-23 06:40:11 +03:00
htfab
d497541361
fix: handle PDK_ROOT being unset for the docker command line
2024-09-23 06:40:11 +03:00
htfab
3627058a39
fix: adjust glob pattern for util percentage
2024-09-20 15:30:05 +03:00
htfab
da472a9133
fix: add --docker-no-tty to openlane2 command line
2024-09-20 15:30:05 +03:00
htfab
3079439e81
fix: make openlane2 install the PDK into $PDK_ROOT
2024-09-10 18:46:25 +03:00
Uri Shaked
587b6cb0d0
fix: type error
2024-08-30 11:44:13 +03:00
Uri Shaked
d3ed62bc00
fix(configure): support declaring power ports as inout
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OpenLane 2.1.1 produces a verilog netlist with the power ports declared as "inout", where as 2.0.8 and earlier declared the power ports as "input". Change our scripts to accept "inout" as a valid direction for the power ports.
2024-08-30 11:39:52 +03:00
Zachary Catlin
12b407dea9
Fixed PDK cell doc URLs
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Currently, the links produced by tt_tool.py --print-cell-category
lead to 404s; this commit uses the correct URLs.
Signed-off-by: Zachary Catlin <zec@box255.org >
2024-08-09 07:48:05 -04:00
Uri Shaked
3c88e6eb04
cleanup(website): remove hugo related functionality
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Project pages are now dynamically generated based on the shuttle index.
2024-07-16 15:15:09 +03:00
htfab
8e41bfb1d9
feat(precheck): add support for 3v3 templates
2024-06-24 07:13:00 +03:00
htfab
b36543e651
refactor!(tt_tool): use same dir for wokwi_test as for test
2024-06-06 07:33:49 +03:00
Uri Shaked
6924b7464b
fix: hardening fails with openlane v2024.05.28
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/bin/bash is no longer present in the container image, so we had to remove it from the docker command line
2024-06-02 10:22:53 +03:00
Uri Shaked
c7cd708524
fix: remove support for openlane yaml config
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see https://github.com/TinyTapeout/tt-support-tools/pull/55#issuecomment-2138626540 for reasoning
2024-06-01 17:25:23 +03:00
htfab and htfab
59c9f8e2db
feat: add support for json config files ( #55 )
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* feat: add support for json config files
* feat: make json the preferred config format
* feat: allow yaml config format
* feat!: remove compatibility tweaks for tt07's config.tcl
---------
Co-authored-by: htfab <mpw@htamas.net >
2024-06-01 17:23:33 +03:00
Uri Shaked
11b2d371b4
fix(documentation): exit with error code if PDF generation fails
2024-05-29 17:02:39 +03:00
htfab
2b48c36ecb
fix: remove progress bar in github actions
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It breaks the log as every refresh is shown as a new line.
2024-05-17 20:51:32 +03:00
htfab
a791fde25c
feat: allow hardening with openlane2
2024-05-16 23:34:05 +03:00
matt venn
d8d3836cf8
Update project.py
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fix 'how to use' error message
2024-05-14 15:15:53 +02:00
htfab
c36f3a3615
feat(datasheet): add analog pins to project pdf
2024-05-07 08:47:00 +03:00
htfab
b3321a93c6
feat(datasheet): add analog pins to Project class
2024-05-07 08:47:00 +03:00
htfab
8ddef688df
feat(datasheet): use mustache for project_preview
2024-05-07 08:47:00 +03:00
Uri Shaked
0c171af9b4
feat(fpga): read seed / target frequency from environment
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Read the values from TT_FPGA_SEED / TT_FPGA_FREQ, and default to 12 MHz frequency.
2024-05-01 23:47:35 +03:00
Uri Shaked
b6ec741349
feat(fpga): initial implementation
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Adds a new `tt_tool.py --create-fpga-bitstream` flag that creates a TT Sim FPGA bitstream from the user's project.
2024-05-01 23:13:21 +03:00
Uri Shaked
60c8ff8b8e
fix(configure): update synth stats paths for tt06
2024-04-26 12:23:38 +03:00
htfab
bc500a3a56
fix(docs): remove text labels from subcells in png
2024-04-17 14:29:49 +03:00
Uri Shaked
d5153c3f22
fix(tt_tool): clock issue warnings break with custom openlane configs
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they break when some of the steps are disabled, e.g. https://github.com/iic-jku/jku-tt06-tdc-v2/
2024-04-13 20:31:27 +02:00
Uri Shaked
9c7ebcb731
feat(tt_tool): display clock issue warnings #34
2024-04-08 15:10:47 +03:00
Uri Shaked
16fb26f5e6
fix(datasheet): images missing #32
2024-04-08 15:04:28 +03:00