mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
108 lines
3.2 KiB
JSON
108 lines
3.2 KiB
JSON
{
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"DESIGN_NAME": "user_project_wrapper",
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"VERILOG_FILES": [
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"dir::../../verilog/rtl/defines.v",
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"dir::../../verilog/rtl/user_project_wrapper.v"
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],
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"ROUTING_CORES": 8,
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"CLOCK_PERIOD": 25,
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"CLOCK_PORT": "wb_clk_i",
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"CLOCK_NET": "mprj.clk",
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"FP_PDN_MACRO_HOOKS": [],
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"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
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"PDN_CFG": "dir::pdn_cfg.tcl",
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"MAGIC_DEF_LABELS": 0,
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"VERILOG_FILES_BLACKBOX": [
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"dir::../../verilog/rtl/defines.v",
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"dir::../../verilog/blackbox_project_includes.v"
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],
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"EXTRA_LEFS": [],
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"EXTRA_GDS_FILES": [],
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"BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
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"RUN_KLAYOUT_XOR": 0,
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"RUN_KLAYOUT_DRC": 0,
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"RUN_MAGIC_DRC": 0,
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"IO_SYNC": 0,
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"FP_PDN_CHECK_NODES": 0,
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"SYNTH_ELABORATE_ONLY": 1,
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"PL_RANDOM_GLB_PLACEMENT": 1,
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"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
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"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
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"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
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"FP_PDN_ENABLE_RAILS": 0,
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"DIODE_INSERTION_STRATEGY": 0,
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"RUN_FILL_INSERTION": 0,
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"RUN_TAP_DECAP_INSERTION": 0,
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"FP_PDN_VPITCH": 140,
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"FP_PDN_VOFFSET": 186,
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"FP_PDN_HPITCH": 185,
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"FP_PDN_HOFFSET": 130,
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"CLOCK_TREE_SYNTH": 0,
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"MAGIC_ZEROIZE_ORIGIN": 0,
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"FP_SIZING": "absolute",
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"RUN_CVC": 0,
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"UNIT": 2.4,
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"FP_IO_VEXTEND": "expr::2 * $UNIT",
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"FP_IO_HEXTEND": "expr::2 * $UNIT",
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"FP_IO_VLENGTH": "expr::$UNIT",
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"FP_IO_HLENGTH": "expr::$UNIT",
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"FP_IO_VTHICKNESS_MULT": 4,
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"FP_IO_HTHICKNESS_MULT": 4,
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"FP_PDN_CORE_RING": 1,
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"FP_PDN_CORE_RING_VWIDTH": 3.1,
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"FP_PDN_CORE_RING_HWIDTH": 3.1,
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"FP_PDN_CORE_RING_VOFFSET": 12.45,
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"FP_PDN_CORE_RING_HOFFSET": 12.45,
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"FP_PDN_CORE_RING_VSPACING": 1.7,
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"FP_PDN_CORE_RING_HSPACING": 1.7,
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"FP_PDN_VWIDTH": 3.1,
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"FP_PDN_HWIDTH": 3.1,
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"FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
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"FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
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"VDD_NETS": [
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"vccd1",
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"vccd2",
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"vdda1",
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"vdda2"
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],
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"GND_NETS": [
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"vssd1",
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"vssd2",
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"vssa1",
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"vssa2"
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],
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"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
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"pdk::sky130*": {
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"RT_MAX_LAYER": "met4",
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"DIE_AREA": "0 0 2920 3520",
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"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
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"scl::sky130_fd_sc_hd": {
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"CLOCK_PERIOD": 25
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},
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"scl::sky130_fd_sc_hdll": {
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"CLOCK_PERIOD": 10
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},
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"scl::sky130_fd_sc_hs": {
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"CLOCK_PERIOD": 8
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},
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"scl::sky130_fd_sc_ls": {
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"CLOCK_PERIOD": 10,
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"SYNTH_MAX_FANOUT": 5
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},
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"scl::sky130_fd_sc_ms": {
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"CLOCK_PERIOD": 10
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}
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},
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"pdk::gf180mcuC": {
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"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
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"FP_PDN_CHECK_NODES": 0,
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"FP_PDN_ENABLE_RAILS": 0,
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"RT_MAX_LAYER": "Metal4",
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"DIE_AREA": "0 0 3000 3000",
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"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
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"PL_OPENPHYSYN_OPTIMIZATIONS": 0,
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"DIODE_INSERTION_STRATEGY": 0,
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"MAGIC_WRITE_FULL_LEF": 0
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}
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}
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