Uri Shaked
ef96fa4e1b
fix(precheck): incorrect minimum power rail width for ihp-sg13g2
2025-12-11 19:41:59 +02:00
Uri Shaked
9f7195a42d
feat(tech/gf180mcuD): copy corner logos to all metal layers
2025-12-08 12:54:14 +02:00
Uri Shaked
853872f0e2
perf(tech/gf180mcuD): optimize corner logo GDS files
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Generate optimized polygons instead of generating a rect for each pixel from the source PNG image.
2025-12-07 20:49:39 +02:00
Uri Shaked
9552777451
feat(tech/gf180mcuD): tt corner logo
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Add the Tiny Tapeout logo to the top-left corner to the chip
2025-12-07 11:23:31 +02:00
Uri Shaked
77d9b04539
fix(tech/gf180mcuD): pmndmy offgrid DRC violations in the tillitis corner logo
2025-12-06 17:16:01 +02:00
Uri Shaked
deda2f4f7f
fix(tech/gf180mcuD): tillitis corner logo DRC violations
2025-12-05 21:36:11 +02:00
Uri Shaked
8b011af876
feat(tech/gf180mcuD): die corner logos
2025-12-05 20:20:03 +02:00
Uri Shaked
b57f798ec4
fix(precheck): disable additional min density checks for ihp-sg13g2
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Disable GatPoly, Activ, and TopMetal2 min density checks
2025-12-05 10:00:44 +02:00
Uri Shaked
de6544ea80
fix(precheck): hardcoded layer name in error message
2025-12-05 09:23:34 +02:00
Uri Shaked
bbd9aa1821
fix(tech/gf180mcuD): scale logo to 65 um
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The current size, 100 um, is wider than the mux spine, so it doesn't fit.
2025-11-25 18:24:45 +02:00
Uri Shaked
45eb4a6b5d
fix(precheck): update sg13g2_mr deck to be compatible with klayout 0.30
2025-11-24 14:38:39 +02:00
Uri Shaked
c813d4796a
fix(precheck): adapt for new IHP def files
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TopMetal1 is allowed now, and the power pins moved from Metal5 to TopMetal1.
2025-11-24 14:20:04 +02:00
Uri Shaked
6d72ed6d6a
fix(tech/ihp): add new standard cells
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The ihp-sg13g2 PDK has recently added 6 new standard cells variants in IHP-GmbH/IHP-Open-PDK#553 .
2025-11-23 20:16:31 +02:00
Uri Shaked
c35546a7e4
feat(tech/ihp-sg13g2): update user project .def files
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This change moves the power rails to TopMetal1, and makes the TopMetal1 layer available for the user designs.
In addition, we now let LibreLane install the PDK instead of having to install it separately.
2025-11-23 19:13:21 +02:00
Uri Shaked
5f2a734ef9
feat(configure): support for multiple mux config files in TT_CONFIG
2025-11-20 11:13:11 +02:00
Uri Shaked
ef5191cec2
fix(configure): typo in warning message
2025-11-20 10:37:56 +02:00
Uri Shaked
e80e10658b
feat(configure): add --create-foundry-submission option
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Replaces the old `--create-chipfoundry-submission` and `--create-ihp-submission` options, and will also be used for wafer.space submissions.
Also include an .oas submission file in the foundry_submission directory (in addition to the existing gds submission file)
2025-11-18 13:27:53 +02:00
Uri Shaked
75efd78187
feat(tech/gf180mcuD): disable copying of power gate macros
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They do not exist yet for gf180mcuD
2025-11-17 21:49:14 +02:00
Uri Shaked
b1d2cf29b2
fix(rom): disable KLayout DRC for gf180mcuD
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It seems to be broken ATM
2025-11-17 21:48:45 +02:00
Uri Shaked
65da0fc1a3
feat(rom): gf180mcuD config
2025-11-17 21:09:50 +02:00
Uri Shaked
2121978263
feat(tech/gf180mcuD): another def files update
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This is the template using the half pitch offset that's currently used following the PDK's tracks.info.
2025-11-16 13:24:16 +02:00
Uri Shaked
5c4503072e
feat(precheck): oas file support #134
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replace legacy .gds.br support with .oas file support
2025-11-16 10:04:22 +02:00
Uri Shaked
f5d9968a40
feat(tech/gf180mcuD): update .def files
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Pin positions shifted to support for future power gate
2025-11-16 09:25:30 +02:00
Uri Shaked
aad3efd7a1
fix(configure): remove legacy sta code
2025-11-15 21:31:38 +02:00
Uri Shaked
93e7e2971f
fix(shuttle): backward compatibility ttsky25a mux macro names
2025-11-09 10:34:05 +02:00
Uri Shaked
bb9107ee87
fix: remove cocotb from requirements
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It's only needed by the wokwi testing library, and it causes version conflicts with the user/tt-multiplexer provided cocotb versions.
2025-11-09 09:41:10 +02:00
Uri Shaked
b1fca8f72d
chore(precheck): update klayout sky130A DRC deck
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following chipfoundry/mpw_precheck#101
2025-11-08 08:48:14 +02:00
Uri Shaked
eebefdd779
feat(logo): gf180mcuD support
2025-11-06 11:23:14 +02:00
Uri Shaked
bee33c5d9d
fix(rom): add "g" to 7-segment alphabet
2025-11-06 11:13:39 +02:00
Uri Shaked
03ca42307f
feat(tt_tools): --check-docs now prints all errors
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Previously, it only printed the first error it encountered, causing more iterations when fixing info.yaml and info.md errors
2025-10-03 18:25:42 +03:00
Uri Shaked
bdff4ca192
ci: include test results in action summary
2025-10-03 17:54:57 +03:00
Uri Shaked
a9e829d0c1
test: info.yaml validation tests
2025-10-03 17:50:58 +03:00
Uri Shaked
29e6a05555
cleanup: remove .gds.br support
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We now use .oas instead
2025-10-02 08:11:37 +03:00
Uri Shaked
131f64cecb
feat(tt_tool): --open-in-openroad and --open-in-klayout flags #113
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close #113
2025-10-01 22:53:37 +03:00
Uri Shaked
7d5a6b229f
fix(tt_tool): use correct timing data for gf180mcuD
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We are targeting 3.3V, but until now we used 5V timing data.
2025-09-30 15:47:56 +03:00
Uri Shaked
65b404f80a
Merge pull request #119 from TinyTapeout/gf180mcu
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Initial support for the gf180mcuD PDK (with wafer.space)
2025-09-29 20:26:35 +03:00
Uri Shaked
1b336f4996
feat(tt_tool): cell/category definitions for gf180mcuD
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Enables the --print-cell-summary and --print-cell-category commands for gf projects
2025-09-29 16:17:23 +03:00
Uri Shaked
0afaaef4d4
ci(test-harden): add gf180mcuD
2025-09-29 16:17:23 +03:00
Uri Shaked
fcf7e8a37f
fix(tt_tool): always specify the power pin names
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Up to this point, we relied on the PDK's default power pin names. However, the defaults names for GF180, VDD and VSS, are not compatible with Tiny Tapeout, which expects VPWR (or VDPWR) and VGND. So instead, we set the VDD_PIN and GND_PIN config options explicitly.
2025-09-29 16:17:23 +03:00
Uri Shaked
1ab2abc8d5
feat: initial gf180mcuD support
2025-09-29 16:17:14 +03:00
Uri Shaked
44d164955d
fix(precheck): read the PDK name from the PDK environment variable
2025-09-29 16:16:20 +03:00
Uri Shaked
8a36225bdb
feat(tt_util): create a pdk.json file with pdk name / version info
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This file replaces the old "FLOW_VERSION" and "PDK_SOURCES"
2025-09-29 16:14:55 +03:00
Uri Shaked
d14142e412
fix(tt_tool): create merged config right after creating user config
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This allows users to simply run `--create-user-config` and then manually harden with librelane using the generated config file.
2025-09-25 12:57:37 +03:00
Uri Shaked
fcb93fde4a
fix: remove ".mk" config format support
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It was a temporary hack to support OpenROAD-flow-scripts (ORFS) for early IHP shuttles
2025-09-25 12:55:08 +03:00
Uri Shaked
9056f14ddc
feat(tt_tool): set TT_PDK in user project OAS file
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The TT_PDK property will be set to the PDK used to harden the project
2025-09-25 09:42:07 +03:00
Uri Shaked
7732914248
fix(tech/sky130A): remove ROW and TRACK lines from .def files
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LibreLane runs happily without them, but they cause issue when using a different standard cell library (e.g. hs instead of the default hd).
2025-09-24 22:36:24 +03:00
Uri Shaked
c4892189f9
chore: upgrade cocotb, pytest
2025-09-23 16:38:27 +03:00
Uri Shaked
305f3ecaf8
fix(tt_tool): vary RT_MAX_LAYER per tech
...
Each tech has a different metal stackup, so user projects get a different top routing metal layer. tt-support-tools now handles this instead of the user having to worry about this when switching PDKs.
2025-09-18 11:45:44 +03:00
Uri Shaked
84efb79dd7
feat(tt_tool): --create-tt-submission command
2025-09-18 11:36:03 +03:00
Uri Shaked
ae0894906a
Merge pull request #115 from TinyTapeout/tech-refactor
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Refactor to separate PDK/tech-specific code
2025-09-14 14:51:28 +03:00
Uri Shaked
0529b699de
fix(precheck): rename "sky130" to "sky130A"
...
Keep the tech naming consistent with the rest of tt-support-tools code
2025-09-13 20:28:54 +03:00
Uri Shaked
498e098f9a
refactor(rom): unified librelane config with per-PDK overrides
2025-09-13 20:28:54 +03:00
Uri Shaked
28fd25f684
refactor: separate tech specific code
...
Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
2025-09-13 20:28:48 +03:00
Uri Shaked
c67d54ee54
fix(tt_tool): routing stats broken for LibreLane 3.x
2025-09-09 16:14:57 +03:00
Uri Shaked
dc0f9c87b4
ci(test-harden): GH action that tests GDS hardening
2025-09-09 16:14:27 +03:00
Uri Shaked
4347c961d0
refactor(tt_tool): openlane2 -> librelane
2025-09-08 17:51:13 +03:00
Uri Shaked
5e9fff900e
cleanup: remove legacy code
2025-09-08 16:02:33 +03:00
Uri Shaked
278718ca12
chore: update efabless -> chipfoundry
2025-09-08 15:44:33 +03:00
Uri Shaked
9788d3d545
fix(rom): use DECAP_CELL settings from PDK
2025-09-08 15:44:32 +03:00
Uri Shaked
9024d9ff0e
fix(rom): extend 7-segment alphabet
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Add "c", "a", "d" and "s", "k", "y" to the 7-segment encoding dictionary, make "H" and "I" uppercase (so IHP is rendered uppercase and not lowercase)
2025-09-08 15:44:27 +03:00
Uri Shaked
ef2b0de84b
fix(configure): fails due to missing args.pdk
...
slightly refactor project.py to make the code more extensible to future PDK support
2025-09-02 17:42:28 +03:00
Uri Shaked
9519fa87fd
fix(tt_tool): project tile configuration always checked against SKY130 tile sizes
2025-09-02 17:20:02 +03:00
Uri Shaked
9a59843db0
style(fpga): python code formatting issues
2025-09-02 17:11:26 +03:00
Uri Shaked
a95630a378
feat(ihp): add 6x4 template
2025-09-02 17:07:57 +03:00
Uri Shaked
68e2a49925
feat(logo): corner logo for IHP
2025-08-20 10:48:28 +03:00
Uri Shaked
58807a2145
feat(logo): IHP shuttle support
2025-08-19 23:14:09 +03:00
Uri Shaked
d69a0eac0c
fix(logo): support to longer shuttle names (e.g. TTCAD25a)
2025-08-19 23:13:26 +03:00
Uri Shaked
2675235ea2
fix(shuttle): don't copy pg macros when copying final results
...
There is no real reason to copy them, and they vary per shuttle type
2025-08-19 22:14:41 +03:00
Uri Shaked
bafe03504f
feat(shuttle): ihp power switch support
2025-08-19 16:26:05 +03:00
Uri Shaked
10e2f1108c
feat(shuttle): report missing muxes
...
When we have x4-tile high projects, some muxes will be missing. Report them as such in the shuttle index, so that the shuttle map on the website displays correctly.
2025-08-15 20:12:32 +03:00
Uri Shaked
62f5e45102
fix: mistune type errors
2025-08-15 20:12:27 +03:00
Uri Shaked
bebe93d93b
fix(precheck): add HeatRes.drawing to list of valid IHP SG13G2 layers
2025-05-09 22:26:37 +03:00
Uri Shaked
0baf1ece4b
feat(precheck): IHP KLayout DRC
2025-04-16 17:56:01 +03:00
Uri Shaked
fe543406d6
fix(precheck): disable power pin check for IHP
...
IHP provided verilog models do not have power ports, so we don't use powered netlists, and thus no need to check for power pins in the GL verilog.
2025-04-16 17:12:34 +03:00
Uri Shaked
746789020e
fix(precheck): update valid list of IHP SG13G2 layers
...
List given by @smunaut
2025-04-16 16:58:45 +03:00
Uri Shaked
c350c2ed16
feat(precheck): initial IHP support
...
still missing the IHP Klayout DRC deck
2025-04-16 08:28:51 +03:00
Uri Shaked
49b57ea0bb
fix: TinyTapeout -> Tiny Tapeout
2025-04-14 09:40:58 +03:00
Uri Shaked
f3b7f15acd
docs: update credits for ihp shuttles
2025-03-31 19:20:35 +03:00
Uri Shaked
6bb8082f65
cleanup(rom): remove old build script
2025-03-30 12:56:39 +03:00
Uri Shaked
0985eb1d46
feat(rom): support for reading sequentially
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This helps in case where some of the `ui_in` pins can't be set due to a plugged-in Pmod or other conflicting driver.
2025-02-02 11:13:48 +02:00
Uri Shaked
8f2ff888d6
style(rom): format verilog code with verible
2025-02-02 10:48:37 +02:00
Uri Shaked
a48b1c7446
feat(configure): support for brotli-compressed GDS files
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Recently, we started compressing GDS files larger than 25 MB due to GitHub REST API blob size limitations.
2024-11-05 14:56:53 +02:00
Uri Shaked
b176ed7ced
feat(orfs): allow overriding PDN config
2024-10-25 10:02:14 +03:00
Uri Shaked
05f4c62dc1
feat(configure): add no_power_gating configuration
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When set, it configures all user projects with `pg_vdd: false`. This is for ihp0p2 shuttle, which doesn't have power gating yet (tt-multiplexer defaults to enable the pg when `pg_vdd` is not explicitly specified).
2024-10-22 11:50:26 +03:00
Uri Shaked
d1e8e31569
feat(configure): add --create-ihp-submission command
...
similar to create-efabless-submission, but uses the ihp directory and skips copying user_defines.v
2024-10-21 21:53:54 +03:00
Uri Shaked
f3e3861176
fix(shuttle): missing powered GL netlists for IHP
...
Hardening requires powered netlists, GL required unpowered netlists. So now we keep both.
2024-10-21 16:53:14 +03:00
Uri Shaked
4eb37893cb
fix(configure): fails on ihp user submissions
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IHP submissions do not have powered netlists, so add a flag to specify that in the shuttles config.yaml file.
2024-10-21 16:01:33 +03:00
Uri Shaked
9dc2af14c8
feat(configure): make top_level_macro configurable
...
For IHP shuttles, we need "tt_ihp_wrapper" instead of "openframe_project_wrapper"
2024-10-21 13:31:51 +03:00
Uri Shaked
cbbf76df98
feat(rom): ihp hardening support
2024-10-21 10:09:05 +03:00
Uri Shaked
474b576b3e
fix(rom): fails to build on ihp shuttles
...
Add "i", "h", "p" to the 7-segment encoding dictionary.
2024-10-20 23:44:55 +03:00
Uri Shaked
07e91d894b
chore: upgrade cocotb to 1.9.1 #69
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cocotb==1.8.1 fails building on macOS ARM-based systems. More recent versions build successfully.
resolves #69
2024-09-27 12:19:45 +03:00
Uri Shaked
96f3577cad
chore(precheck): update klayout DRC deck
...
following efabless/mpw_precheck#289
2024-09-11 23:39:59 +03:00
Uri Shaked
4b04660726
fix(reharden): support new shuttle index format (v3)
2024-09-09 23:19:15 +03:00
Uri Shaked
587b6cb0d0
fix: type error
2024-08-30 11:44:13 +03:00
Uri Shaked
d3ed62bc00
fix(configure): support declaring power ports as inout
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OpenLane 2.1.1 produces a verilog netlist with the power ports declared as "inout", where as 2.0.8 and earlier declared the power ports as "input". Change our scripts to accept "inout" as a valid direction for the power ports.
2024-08-30 11:39:52 +03:00
Uri Shaked
3c88e6eb04
cleanup(website): remove hugo related functionality
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Project pages are now dynamically generated based on the shuttle index.
2024-07-16 15:15:09 +03:00
Uri Shaked
63eb3d550f
feat(configure): copy tt_pg_1v8_4 macro
2024-07-04 22:17:53 +03:00
Uri Shaked
054e41b839
feat(configure): set "pg_vaa" in modules.yaml for 3v3 projects
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This property tells the mux to include 3v3 power gate (in addition to the standard 1v8 power gate)
2024-07-04 21:38:40 +03:00
Uri Shaked
3c25ae08a6
feat(analog): magic script to create a new analog project
2024-06-26 21:22:52 +03:00
Uri Shaked
674fdc7ef7
fix(precheck): update analog template paths
2024-06-18 14:29:40 +03:00